diff options
Diffstat (limited to 'host/lib')
| -rw-r--r-- | host/lib/rfnoc/dma_fifo_block_ctrl_impl.cpp | 6 | ||||
| -rw-r--r-- | host/lib/usrp/cores/dma_fifo_core_3000.cpp | 17 | ||||
| -rw-r--r-- | host/lib/usrp/cores/dma_fifo_core_3000.hpp | 2 |
3 files changed, 17 insertions, 8 deletions
diff --git a/host/lib/rfnoc/dma_fifo_block_ctrl_impl.cpp b/host/lib/rfnoc/dma_fifo_block_ctrl_impl.cpp index 93f599314..2a5117149 100644 --- a/host/lib/rfnoc/dma_fifo_block_ctrl_impl.cpp +++ b/host/lib/rfnoc/dma_fifo_block_ctrl_impl.cpp @@ -23,13 +23,11 @@ #include <uhd/types/wb_iface.hpp> #include <boost/make_shared.hpp> #include <boost/thread/mutex.hpp> +#include <boost/format.hpp> using namespace uhd; using namespace uhd::rfnoc; -//TODO (Ashish): This should come from the framework -static const double BUS_CLK_RATE = 166.67e6; - class dma_fifo_block_ctrl_impl : public dma_fifo_block_ctrl { public: @@ -70,7 +68,7 @@ public: if (bisterr != 0) { throw uhd::runtime_error(str(boost::format("BIST failed! (code: %d)\n") % bisterr)); } else { - double throughput = _perifs[i].core->get_bist_throughput(BUS_CLK_RATE); + double throughput = _perifs[i].core->get_bist_throughput(); UHD_LOGGER_INFO("RFNOC") << (boost::format("pass (Throughput: %.1fMB/s)") % (throughput/1e6)) ; } } else { diff --git a/host/lib/usrp/cores/dma_fifo_core_3000.cpp b/host/lib/usrp/cores/dma_fifo_core_3000.cpp index 18c79f4c5..b80ce62d8 100644 --- a/host/lib/usrp/cores/dma_fifo_core_3000.cpp +++ b/host/lib/usrp/cores/dma_fifo_core_3000.cpp @@ -20,7 +20,7 @@ #include <boost/thread/thread.hpp> //sleep #include <uhd/utils/soft_register.hpp> #include <uhd/utils/log.hpp> - +#include <boost/format.hpp> using namespace uhd; #define SR_DRAM_BIST_BASE 16 @@ -40,6 +40,7 @@ protected: static const uint32_t RB_BIST_STATUS = 1; static const uint32_t RB_BIST_XFER_CNT = 2; static const uint32_t RB_BIST_CYC_CNT = 3; + static const uint32_t RB_BUS_CLK_RATE = 4; rb_addr_reg_t(uint32_t base): soft_reg32_wo_t(base + 0) @@ -214,6 +215,14 @@ public: return (static_cast<double>(xfer_cnt)/cyc_cnt); } + double get_bus_clk_rate() { + uint32_t bus_clk_rate = 0; + boost::lock_guard<boost::mutex> lock(_mutex); + _addr_reg.write(rb_addr_reg_t::ADDR, rb_addr_reg_t::RB_BUS_CLK_RATE); + bus_clk_rate = _iface->peek32(_rb_addr); + return (static_cast<double>(bus_clk_rate)); + } + private: wb_iface::sptr _iface; rb_addr_reg_t _addr_reg; @@ -326,11 +335,13 @@ public: return _fifo_readback.get_bist_status().error; } - virtual double get_bist_throughput(double fifo_clock_rate) { + virtual double get_bist_throughput() { if (_has_ext_bist) { _wait_for_bist_done(1000); static const double BYTES_PER_CYC = 8; - return _fifo_readback.get_xfer_ratio() * fifo_clock_rate * BYTES_PER_CYC; + double bus_clk_rate = _fifo_readback.get_bus_clk_rate(); + UHD_LOGGER_INFO("DEBUG") << boost::format("[DMA FIFO] Clock rate for BIST calculation: %d ") % bus_clk_rate; + return _fifo_readback.get_xfer_ratio() * bus_clk_rate * BYTES_PER_CYC; } else { throw uhd::not_implemented_error( "dma_fifo_core_3000: Throughput counter only available on FPGA images with extended BIST enabled"); diff --git a/host/lib/usrp/cores/dma_fifo_core_3000.hpp b/host/lib/usrp/cores/dma_fifo_core_3000.hpp index 46a913c93..55a126f76 100644 --- a/host/lib/usrp/cores/dma_fifo_core_3000.hpp +++ b/host/lib/usrp/cores/dma_fifo_core_3000.hpp @@ -79,7 +79,7 @@ public: /*! * Get the throughput measured from the last invocation of the BIST (extended BIST only) */ - virtual double get_bist_throughput(double fifo_clock_rate) = 0; + virtual double get_bist_throughput() = 0; }; |