diff options
Diffstat (limited to 'host/lib/usrp/common')
| -rw-r--r-- | host/lib/usrp/common/ad9361_ctrl.cpp | 2 | ||||
| -rw-r--r-- | host/lib/usrp/common/ad9361_driver/ad9361_device.cpp | 1428 | ||||
| -rw-r--r-- | host/lib/usrp/common/ad936x_manager.cpp | 2 | ||||
| -rw-r--r-- | host/lib/usrp/common/adf4001_ctrl.cpp | 157 | ||||
| -rw-r--r-- | host/lib/usrp/common/adf435x.cpp | 4 | ||||
| -rw-r--r-- | host/lib/usrp/common/apply_corrections.cpp | 139 | ||||
| -rw-r--r-- | host/lib/usrp/common/fx2_ctrl.cpp | 241 | ||||
| -rw-r--r-- | host/lib/usrp/common/io_service_args.cpp | 13 | ||||
| -rw-r--r-- | host/lib/usrp/common/io_service_mgr.cpp | 25 | ||||
| -rw-r--r-- | host/lib/usrp/common/lmx2592.cpp | 391 | ||||
| -rw-r--r-- | host/lib/usrp/common/recv_packet_demuxer.cpp | 88 | ||||
| -rw-r--r-- | host/lib/usrp/common/validate_subdev_spec.cpp | 82 |
12 files changed, 1339 insertions, 1233 deletions
diff --git a/host/lib/usrp/common/ad9361_ctrl.cpp b/host/lib/usrp/common/ad9361_ctrl.cpp index 2c928efcc..a584ef0f7 100644 --- a/host/lib/usrp/common/ad9361_ctrl.cpp +++ b/host/lib/usrp/common/ad9361_ctrl.cpp @@ -9,8 +9,8 @@ #include <uhd/types/serial.hpp> #include <uhd/utils/log.hpp> #include <uhdlib/usrp/common/ad9361_ctrl.hpp> -#include <memory> #include <cstring> +#include <memory> #include <mutex> using namespace uhd; diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp index 44b650f52..784658cb0 100644 --- a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp +++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp @@ -5,22 +5,21 @@ // SPDX-License-Identifier: GPL-3.0-or-later // +#include "ad9361_device.h" +#include "ad9361_client.h" #include "ad9361_filter_taps.h" #include "ad9361_gain_tables.h" #include "ad9361_synth_lut.h" -#include "ad9361_client.h" -#include "ad9361_device.h" #define _USE_MATH_DEFINES #include <uhd/exception.hpp> #include <uhd/utils/log.hpp> - -#include <boost/scoped_array.hpp> +#include <stdint.h> #include <boost/format.hpp> #include <boost/math/special_functions.hpp> +#include <boost/scoped_array.hpp> #include <chrono> -#include <thread> #include <cmath> -#include <stdint.h> +#include <thread> //////////////////////////////////////////////////////////// // the following macros evaluate to a compile time constant @@ -33,14 +32,11 @@ #define HEX__(n) 0x##n##LU /* 8-bit conversion function */ -#define B8__(x) ((x&0x0000000FLU)?1:0) \ -+((x&0x000000F0LU)?2:0) \ -+((x&0x00000F00LU)?4:0) \ -+((x&0x0000F000LU)?8:0) \ -+((x&0x000F0000LU)?16:0) \ -+((x&0x00F00000LU)?32:0) \ -+((x&0x0F000000LU)?64:0) \ -+((x&0xF0000000LU)?128:0) +#define B8__(x) \ + ((x & 0x0000000FLU) ? 1 : 0) + ((x & 0x000000F0LU) ? 2 : 0) \ + + ((x & 0x00000F00LU) ? 4 : 0) + ((x & 0x0000F000LU) ? 8 : 0) \ + + ((x & 0x000F0000LU) ? 16 : 0) + ((x & 0x00F00000LU) ? 32 : 0) \ + + ((x & 0x0F000000LU) ? 64 : 0) + ((x & 0xF0000000LU) ? 128 : 0) /* for upto 8-bit binary constants */ #define B8(d) ((unsigned char)B8__(HEX__(d))) @@ -53,8 +49,9 @@ namespace uhd { namespace usrp { * point numbers. It is used to prevent re-tunes for frequencies that are * the same but not 'exactly' because of data precision issues. */ // TODO: see if we can avoid the need for this function -int freq_is_nearly_equal(double a, double b) { - return std::max(a,b) - std::min(a,b) < 1; +int freq_is_nearly_equal(double a, double b) +{ + return std::max(a, b) - std::min(a, b) < 1; } /*********************************************************************** @@ -63,26 +60,29 @@ int freq_is_nearly_equal(double a, double b) { /* This function takes in the calculated maximum number of FIR taps, and * returns a number of taps that makes AD9361 happy. */ -int get_num_taps(int max_num_taps) { - - int num_taps = 0; +int get_num_taps(int max_num_taps) +{ + int num_taps = 0; int num_taps_list[] = {16, 32, 48, 64, 80, 96, 112, 128}; int i; - for(i = 1; i < 8; i++) { - if(max_num_taps >= num_taps_list[i]) { + for (i = 1; i < 8; i++) { + if (max_num_taps >= num_taps_list[i]) { continue; } else { num_taps = num_taps_list[i - 1]; break; } - } if(num_taps == 0) { num_taps = 128; } + } + if (num_taps == 0) { + num_taps = 128; + } return num_taps; } -const double ad9361_device_t::AD9361_MAX_GAIN = 89.75; -const double ad9361_device_t::AD9361_MIN_CLOCK_RATE = 220e3; -const double ad9361_device_t::AD9361_MAX_CLOCK_RATE = 61.44e6; +const double ad9361_device_t::AD9361_MAX_GAIN = 89.75; +const double ad9361_device_t::AD9361_MIN_CLOCK_RATE = 220e3; +const double ad9361_device_t::AD9361_MAX_CLOCK_RATE = 61.44e6; const double ad9361_device_t::AD9361_CAL_VALID_WINDOW = 100e6; // Max bandwdith is due to filter rolloff in analog filter stage const double ad9361_device_t::AD9361_MIN_BW = 200e3; @@ -98,7 +98,8 @@ const double ad9361_device_t::DEFAULT_TX_FREQ = 850e6; * how many taps are in the filter, and given a vector of the taps * themselves. */ -void ad9361_device_t::_program_fir_filter(direction_t direction, chain_t chain, int num_taps, uint16_t *coeffs) +void ad9361_device_t::_program_fir_filter( + direction_t direction, chain_t chain, int num_taps, uint16_t* coeffs) { uint16_t base; @@ -115,14 +116,14 @@ void ad9361_device_t::_program_fir_filter(direction_t direction, chain_t chain, uint8_t reg_chain = 0; switch (chain) { - case CHAIN_1: - reg_chain = 0x01 << 3; - break; - case CHAIN_2: - reg_chain = 0x02 << 3; - break; - default: - reg_chain = 0x03 << 3; + case CHAIN_1: + reg_chain = 0x01 << 3; + break; + case CHAIN_2: + reg_chain = 0x02 << 3; + break; + default: + reg_chain = 0x03 << 3; } /* Turn on the filter clock. */ @@ -140,7 +141,8 @@ void ad9361_device_t::_program_fir_filter(direction_t direction, chain_t chain, _io_iface->poke8(base + 4, 0x00); } - /* Iterate through indirect programming of filter coeffs using ADI recomended procedure */ + /* Iterate through indirect programming of filter coeffs using ADI recomended + * procedure */ for (addr = 0; addr < num_taps; addr++) { _io_iface->poke8(base + 0, addr); _io_iface->poke8(base + 1, (coeffs[addr]) & 0xff); @@ -151,23 +153,25 @@ void ad9361_device_t::_program_fir_filter(direction_t direction, chain_t chain, } /* UG-671 states (page 25) (paraphrased and clarified): - " After the table has been programmed, write to register BASE+5 with the write bit D2 cleared and D1 high. - Then, write to register BASE+5 again with D1 clear, thus ensuring that the write bit resets internally - before the clock stops. Wait 4 sample clock periods after setting D2 high while that data writes into the table" + " After the table has been programmed, write to register BASE+5 with the write bit D2 + cleared and D1 high. Then, write to register BASE+5 again with D1 clear, thus + ensuring that the write bit resets internally before the clock stops. Wait 4 sample + clock periods after setting D2 high while that data writes into the table" */ _io_iface->poke8(base + 5, reg_numtaps | reg_chain | (1 << 1)); if (direction == RX) { - _io_iface->poke8(base + 5, reg_numtaps | reg_chain ); + _io_iface->poke8(base + 5, reg_numtaps | reg_chain); /* Rx Gain, set to prevent digital overflow/saturation in filters 0:+6dB, 1:0dB, 2:-6dB, 3:-12dB page 35 of UG-671 */ - _io_iface->poke8(base + 6, 0x02); /* Also turn on -6dB Rx gain here, to stop filter overfow.*/ + _io_iface->poke8( + base + 6, 0x02); /* Also turn on -6dB Rx gain here, to stop filter overfow.*/ } else { /* Tx Gain. bit[0]. set to prevent digital overflow/saturation in filters 0: 0dB, 1:-6dB page 25 of UG-671 */ - _io_iface->poke8(base + 5, reg_numtaps | reg_chain ); + _io_iface->poke8(base + 5, reg_numtaps | reg_chain); } } @@ -175,26 +179,31 @@ void ad9361_device_t::_program_fir_filter(direction_t direction, chain_t chain, /* Program the RX FIR Filter. */ void ad9361_device_t::_setup_rx_fir(size_t num_taps, int32_t decimation) { - if (not (decimation == 1 or decimation == 2 or decimation == 4)) { + if (not(decimation == 1 or decimation == 2 or decimation == 4)) { throw uhd::runtime_error("[ad9361_device_t] Invalid Rx FIR decimation."); } boost::scoped_array<uint16_t> coeffs(new uint16_t[num_taps]); for (size_t i = 0; i < num_taps; i++) { switch (num_taps) { - case 128: - coeffs[i] = uint16_t((decimation==4) ? fir_128_x4_coeffs[i] : hb127_coeffs[i]); - break; - case 96: - coeffs[i] = uint16_t((decimation==4) ? fir_96_x4_coeffs[i] : hb95_coeffs[i]); - break; - case 64: - coeffs[i] = uint16_t((decimation==4) ? fir_64_x4_coeffs[i] : hb63_coeffs[i]); - break; - case 48: - coeffs[i] = uint16_t((decimation==4) ? fir_48_x4_coeffs[i] : hb47_coeffs[i]); - break; - default: - throw uhd::runtime_error("[ad9361_device_t] Unsupported number of Rx FIR taps."); + case 128: + coeffs[i] = + uint16_t((decimation == 4) ? fir_128_x4_coeffs[i] : hb127_coeffs[i]); + break; + case 96: + coeffs[i] = + uint16_t((decimation == 4) ? fir_96_x4_coeffs[i] : hb95_coeffs[i]); + break; + case 64: + coeffs[i] = + uint16_t((decimation == 4) ? fir_64_x4_coeffs[i] : hb63_coeffs[i]); + break; + case 48: + coeffs[i] = + uint16_t((decimation == 4) ? fir_48_x4_coeffs[i] : hb47_coeffs[i]); + break; + default: + throw uhd::runtime_error( + "[ad9361_device_t] Unsupported number of Rx FIR taps."); } } @@ -204,29 +213,35 @@ void ad9361_device_t::_setup_rx_fir(size_t num_taps, int32_t decimation) /* Program the TX FIR Filter. */ void ad9361_device_t::_setup_tx_fir(size_t num_taps, int32_t interpolation) { - if (not (interpolation == 1 or interpolation == 2 or interpolation == 4)) { + if (not(interpolation == 1 or interpolation == 2 or interpolation == 4)) { throw uhd::runtime_error("[ad9361_device_t] Invalid Tx FIR interpolation."); } if (interpolation == 1 and num_taps > 64) { - throw uhd::runtime_error("[ad9361_device_t] Too many Tx FIR taps for interpolation value."); + throw uhd::runtime_error( + "[ad9361_device_t] Too many Tx FIR taps for interpolation value."); } boost::scoped_array<uint16_t> coeffs(new uint16_t[num_taps]); for (size_t i = 0; i < num_taps; i++) { switch (num_taps) { - case 128: - coeffs[i] = uint16_t((interpolation==4) ? fir_128_x4_coeffs[i] : hb127_coeffs[i]); - break; - case 96: - coeffs[i] = uint16_t((interpolation==4) ? fir_96_x4_coeffs[i] : hb95_coeffs[i]); - break; - case 64: - coeffs[i] = uint16_t((interpolation==4) ? fir_64_x4_coeffs[i] : hb63_coeffs[i]); - break; - case 48: - coeffs[i] = uint16_t((interpolation==4) ? fir_48_x4_coeffs[i] : hb47_coeffs[i]); - break; - default: - throw uhd::runtime_error("[ad9361_device_t] Unsupported number of Tx FIR taps."); + case 128: + coeffs[i] = uint16_t( + (interpolation == 4) ? fir_128_x4_coeffs[i] : hb127_coeffs[i]); + break; + case 96: + coeffs[i] = + uint16_t((interpolation == 4) ? fir_96_x4_coeffs[i] : hb95_coeffs[i]); + break; + case 64: + coeffs[i] = + uint16_t((interpolation == 4) ? fir_64_x4_coeffs[i] : hb63_coeffs[i]); + break; + case 48: + coeffs[i] = + uint16_t((interpolation == 4) ? fir_48_x4_coeffs[i] : hb47_coeffs[i]); + break; + default: + throw uhd::runtime_error( + "[ad9361_device_t] Unsupported number of Tx FIR taps."); } } @@ -310,9 +325,10 @@ void ad9361_device_t::_calibrate_synth_charge_pumps() double ad9361_device_t::_calibrate_baseband_rx_analog_filter(double req_rfbw) { double bbbw = req_rfbw / 2.0; - if(bbbw > _baseband_bw / 2.0) - { - UHD_LOGGER_DEBUG("AD936X")<< "baseband bandwidth too large for current sample rate. Setting bandwidth to: "<<_baseband_bw; + if (bbbw > _baseband_bw / 2.0) { + UHD_LOGGER_DEBUG("AD936X") << "baseband bandwidth too large for current sample " + "rate. Setting bandwidth to: " + << _baseband_bw; bbbw = _baseband_bw / 2.0; } @@ -326,16 +342,17 @@ double ad9361_device_t::_calibrate_baseband_rx_analog_filter(double req_rfbw) } double rxtune_clk = ((1.4 * bbbw * 2 * M_PI) / M_LN2); - _rx_bbf_tunediv = std::min<uint16_t>(511, uint16_t(std::ceil(_bbpll_freq / rxtune_clk))); + _rx_bbf_tunediv = + std::min<uint16_t>(511, uint16_t(std::ceil(_bbpll_freq / rxtune_clk))); _regs.bbftune_config = (_regs.bbftune_config & 0xFE) - | ((_rx_bbf_tunediv >> 8) & 0x0001); + | ((_rx_bbf_tunediv >> 8) & 0x0001); - double bbbw_mhz = bbbw / 1e6; - double temp = ((bbbw_mhz - std::floor(bbbw_mhz)) * 1000) / 7.8125; + double bbbw_mhz = bbbw / 1e6; + double temp = ((bbbw_mhz - std::floor(bbbw_mhz)) * 1000) / 7.8125; uint8_t bbbw_khz = std::min<uint8_t>(127, uint8_t(std::floor(temp + 0.5))); /* Set corner frequencies and dividers. */ - _io_iface->poke8(0x1fb, (uint8_t) (bbbw_mhz)); + _io_iface->poke8(0x1fb, (uint8_t)(bbbw_mhz)); _io_iface->poke8(0x1fc, bbbw_khz); _io_iface->poke8(0x1f8, (_rx_bbf_tunediv & 0x00FF)); _io_iface->poke8(0x1f9, _regs.bbftune_config); @@ -377,9 +394,10 @@ double ad9361_device_t::_calibrate_baseband_tx_analog_filter(double req_rfbw) { double bbbw = req_rfbw / 2.0; - if(bbbw > _baseband_bw / 2.0) - { - UHD_LOGGER_DEBUG("AD936X")<< "baseband bandwidth too large for current sample rate. Setting bandwidth to: "<<_baseband_bw; + if (bbbw > _baseband_bw / 2.0) { + UHD_LOGGER_DEBUG("AD936X") << "baseband bandwidth too large for current sample " + "rate. Setting bandwidth to: " + << _baseband_bw; bbbw = _baseband_bw / 2.0; } @@ -393,9 +411,9 @@ double ad9361_device_t::_calibrate_baseband_tx_analog_filter(double req_rfbw) } double txtune_clk = ((1.6 * bbbw * 2 * M_PI) / M_LN2); - uint16_t txbbfdiv = std::min<uint16_t>(511, uint16_t(std::ceil(_bbpll_freq / txtune_clk))); - _regs.bbftune_mode = (_regs.bbftune_mode & 0xFE) - | ((txbbfdiv >> 8) & 0x0001); + uint16_t txbbfdiv = + std::min<uint16_t>(511, uint16_t(std::ceil(_bbpll_freq / txtune_clk))); + _regs.bbftune_mode = (_regs.bbftune_mode & 0xFE) | ((txbbfdiv >> 8) & 0x0001); /* Program the divider values. */ _io_iface->poke8(0x0d6, (txbbfdiv & 0x00FF)); @@ -432,9 +450,10 @@ double ad9361_device_t::_calibrate_secondary_tx_filter(double req_rfbw) { double bbbw = req_rfbw / 2.0; - if(bbbw > _baseband_bw / 2.0) - { - UHD_LOGGER_DEBUG("AD936X")<< "baseband bandwidth too large for current sample rate. Setting bandwidth to: "<<_baseband_bw; + if (bbbw > _baseband_bw / 2.0) { + UHD_LOGGER_DEBUG("AD936X") << "baseband bandwidth too large for current sample " + "rate. Setting bandwidth to: " + << _baseband_bw; bbbw = _baseband_bw / 2.0; } @@ -459,8 +478,9 @@ double ad9361_device_t::_calibrate_secondary_tx_filter(double req_rfbw) int cap = 0; int i; for (i = 0; i <= 3; i++) { - cap = static_cast<int>(std::floor(0.5 + ((1 / ((corner_freq * res) * 1e6)) * 1e12))) - - 12; + cap = + static_cast<int>(std::floor(0.5 + ((1 / ((corner_freq * res) * 1e6)) * 1e12))) + - 12; if (cap <= 63) { break; @@ -483,7 +503,8 @@ double ad9361_device_t::_calibrate_secondary_tx_filter(double req_rfbw) reg0d0 = 0x57; } else { reg0d0 = 0x00; - throw uhd::runtime_error("[ad9361_device_t] Cal2ndTxFil: INVALID_CODE_PATH bad bbbw_mhz"); + throw uhd::runtime_error( + "[ad9361_device_t] Cal2ndTxFil: INVALID_CODE_PATH bad bbbw_mhz"); } /* Translate resistor values to register settings. */ @@ -528,9 +549,10 @@ double ad9361_device_t::_calibrate_rx_TIAs(double req_rfbw) double bbbw = req_rfbw / 2.0; - if(bbbw > _baseband_bw / 2.0) - { - UHD_LOGGER_DEBUG("AD936X")<< "baseband bandwidth too large for current sample rate. Setting bandwidth to: "<<_baseband_bw; + if (bbbw > _baseband_bw / 2.0) { + UHD_LOGGER_DEBUG("AD936X") << "baseband bandwidth too large for current sample " + "rate. Setting bandwidth to: " + << _baseband_bw; bbbw = _baseband_bw / 2.0; } @@ -545,8 +567,8 @@ double ad9361_device_t::_calibrate_rx_TIAs(double req_rfbw) double ceil_bbbw_mhz = std::ceil(bbbw / 1e6); /* Do some crazy resistor and capacitor math. */ - int Cbbf = (reg1eb * 160) + (reg1ec * 10) + 140; - int R2346 = 18300 * (reg1e6 & 0x07); + int Cbbf = (reg1eb * 160) + (reg1ec * 10) + 140; + int R2346 = 18300 * (reg1e6 & 0x07); double CTIA_fF = (Cbbf * R2346 * 0.56) / 3500; /* Translate baseband BW to register settings. */ @@ -557,22 +579,23 @@ double ad9361_device_t::_calibrate_rx_TIAs(double req_rfbw) } else if (ceil_bbbw_mhz > 10) { reg1db = 0x20; } else { - throw uhd::runtime_error("[ad9361_device_t] CalRxTias: INVALID_CODE_PATH bad bbbw_mhz"); + throw uhd::runtime_error( + "[ad9361_device_t] CalRxTias: INVALID_CODE_PATH bad bbbw_mhz"); } if (CTIA_fF > 2920) { - reg1dc = 0x40; - reg1de = 0x40; - uint8_t temp = (uint8_t) std::min<uint8_t>(127, - uint8_t(std::floor(0.5 + ((CTIA_fF - 400.0) / 320.0)))); + reg1dc = 0x40; + reg1de = 0x40; + uint8_t temp = (uint8_t)std::min<uint8_t>( + 127, uint8_t(std::floor(0.5 + ((CTIA_fF - 400.0) / 320.0)))); reg1dd = temp; reg1df = temp; } else { uint8_t temp = uint8_t(std::floor(0.5 + ((CTIA_fF - 400.0) / 40.0)) + 0x40); - reg1dc = temp; - reg1de = temp; - reg1dd = 0; - reg1df = 0; + reg1dc = temp; + reg1de = temp; + reg1dd = 0; + reg1df = 0; } /* w00t. Settings calculated. Program them and roll out. */ @@ -593,12 +616,12 @@ double ad9361_device_t::_calibrate_rx_TIAs(double req_rfbw) * some of the 40 registers depend on the values in others. */ void ad9361_device_t::_setup_adc() { - double bbbw_mhz = (((_bbpll_freq / 1e6) / _rx_bbf_tunediv) * M_LN2) \ - / (1.4 * 2 * M_PI); + double bbbw_mhz = + (((_bbpll_freq / 1e6) / _rx_bbf_tunediv) * M_LN2) / (1.4 * 2 * M_PI); /* For calibration, baseband BW is half the complex BW, and must be * between 28e6 and 0.2e6. */ - if(bbbw_mhz > 28) { + if (bbbw_mhz > 28) { bbbw_mhz = 28; } else if (bbbw_mhz < 0.20) { bbbw_mhz = 0.20; @@ -606,101 +629,111 @@ void ad9361_device_t::_setup_adc() uint8_t rxbbf_c3_msb = _io_iface->peek8(0x1eb) & 0x3F; uint8_t rxbbf_c3_lsb = _io_iface->peek8(0x1ec) & 0x7F; - uint8_t rxbbf_r2346 = _io_iface->peek8(0x1e6) & 0x07; + uint8_t rxbbf_r2346 = _io_iface->peek8(0x1e6) & 0x07; double fsadc = _adcclock_freq / 1e6; /* Sort out the RC time constant for our baseband bandwidth... */ double rc_timeconst = 0.0; - if(bbbw_mhz < 18) { - rc_timeconst = (1 / ((1.4 * 2 * M_PI) \ - * (18300 * rxbbf_r2346) - * ((160e-15 * rxbbf_c3_msb) - + (10e-15 * rxbbf_c3_lsb) + 140e-15) - * (bbbw_mhz * 1e6))); + if (bbbw_mhz < 18) { + rc_timeconst = + (1 + / ((1.4 * 2 * M_PI) * (18300 * rxbbf_r2346) + * ((160e-15 * rxbbf_c3_msb) + (10e-15 * rxbbf_c3_lsb) + 140e-15) + * (bbbw_mhz * 1e6))); } else { - rc_timeconst = (1 / ((1.4 * 2 * M_PI) \ - * (18300 * rxbbf_r2346) - * ((160e-15 * rxbbf_c3_msb) - + (10e-15 * rxbbf_c3_lsb) + 140e-15) - * (bbbw_mhz * 1e6) * (1 + (0.01 * (bbbw_mhz - 18))))); + rc_timeconst = + (1 + / ((1.4 * 2 * M_PI) * (18300 * rxbbf_r2346) + * ((160e-15 * rxbbf_c3_msb) + (10e-15 * rxbbf_c3_lsb) + 140e-15) + * (bbbw_mhz * 1e6) * (1 + (0.01 * (bbbw_mhz - 18))))); } double scale_res = sqrt(1 / rc_timeconst); double scale_cap = sqrt(1 / rc_timeconst); double scale_snr = (_adcclock_freq < 80e6) ? 1.0 : 1.584893192; - double maxsnr = 640 / 160; + double maxsnr = 640 / 160; /* Calculate the values for all 40 settings registers. * * DO NOT TOUCH THIS UNLESS YOU KNOW EXACTLY WHAT YOU ARE DOING. kthx.*/ uint8_t data[40]; - data[0] = 0; data[1] = 0; data[2] = 0; data[3] = 0x24; - data[4] = 0x24; data[5] = 0; data[6] = 0; - data[7] = std::min<uint8_t>(124, uint8_t(std::floor(-0.5 - + (80.0 * scale_snr * scale_res - * std::min<double>(1.0, sqrt(maxsnr * fsadc / 640.0)))))); + data[0] = 0; + data[1] = 0; + data[2] = 0; + data[3] = 0x24; + data[4] = 0x24; + data[5] = 0; + data[6] = 0; + data[7] = std::min<uint8_t>(124, + uint8_t( + std::floor(-0.5 + + (80.0 * scale_snr * scale_res + * std::min<double>(1.0, sqrt(maxsnr * fsadc / 640.0)))))); double data007 = data[7]; - data[8] = std::min<uint8_t>(255, uint8_t(std::floor(0.5 - + ((20.0 * (640.0 / fsadc) * ((data007 / 80.0)) - / (scale_res * scale_cap)))))); - data[10] = std::min<uint8_t>(127, uint8_t(std::floor(-0.5 + (77.0 * scale_res - * std::min<double>(1.0, sqrt(maxsnr * fsadc / 640.0)))))); + data[8] = std::min<uint8_t>(255, + uint8_t(std::floor(0.5 + + ((20.0 * (640.0 / fsadc) * ((data007 / 80.0)) + / (scale_res * scale_cap)))))); + data[10] = std::min<uint8_t>(127, + uint8_t(std::floor( + -0.5 + + (77.0 * scale_res * std::min<double>(1.0, sqrt(maxsnr * fsadc / 640.0)))))); double data010 = data[10]; - data[9] = std::min<uint8_t>(127, uint8_t(std::floor(0.8 * data010))); - data[11] = std::min<uint8_t>(255, uint8_t(std::floor(0.5 - + (20.0 * (640.0 / fsadc) * ((data010 / 77.0) - / (scale_res * scale_cap)))))); - data[12] = std::min<uint8_t>(127, uint8_t(std::floor(-0.5 - + (80.0 * scale_res * std::min<double>(1.0, - sqrt(maxsnr * fsadc / 640.0)))))); + data[9] = std::min<uint8_t>(127, uint8_t(std::floor(0.8 * data010))); + data[11] = std::min<uint8_t>(255, + uint8_t(std::floor( + 0.5 + + (20.0 * (640.0 / fsadc) * ((data010 / 77.0) / (scale_res * scale_cap)))))); + data[12] = std::min<uint8_t>(127, + uint8_t(std::floor( + -0.5 + + (80.0 * scale_res * std::min<double>(1.0, sqrt(maxsnr * fsadc / 640.0)))))); double data012 = data[12]; - data[13] = std::min<uint8_t>(255, uint8_t(std::floor(-1.5 - + (20.0 * (640.0 / fsadc) * ((data012 / 80.0) - / (scale_res * scale_cap)))))); - data[14] = 21 * uint8_t(std::floor(0.1 * 640.0 / fsadc)); - data[15] = std::min<uint8_t>(127, uint8_t(1.025 * data007)); + data[13] = std::min<uint8_t>(255, + uint8_t(std::floor( + -1.5 + + (20.0 * (640.0 / fsadc) * ((data012 / 80.0) / (scale_res * scale_cap)))))); + data[14] = 21 * uint8_t(std::floor(0.1 * 640.0 / fsadc)); + data[15] = std::min<uint8_t>(127, uint8_t(1.025 * data007)); double data015 = data[15]; - data[16] = std::min<uint8_t>(127, uint8_t(std::floor((data015 - * (0.98 + (0.02 * std::max<double>(1.0, - (640.0 / fsadc) / maxsnr))))))); - data[17] = data[15]; - data[18] = std::min<uint8_t>(127, uint8_t(0.975 * (data010))); + data[16] = std::min<uint8_t>(127, + uint8_t(std::floor( + (data015 + * (0.98 + (0.02 * std::max<double>(1.0, (640.0 / fsadc) / maxsnr))))))); + data[17] = data[15]; + data[18] = std::min<uint8_t>(127, uint8_t(0.975 * (data010))); double data018 = data[18]; - data[19] = std::min<uint8_t>(127, uint8_t(std::floor((data018 - * (0.98 + (0.02 * std::max<double>(1.0, - (640.0 / fsadc) / maxsnr))))))); - data[20] = data[18]; - data[21] = std::min<uint8_t>(127, uint8_t(0.975 * data012)); + data[19] = std::min<uint8_t>(127, + uint8_t(std::floor( + (data018 + * (0.98 + (0.02 * std::max<double>(1.0, (640.0 / fsadc) / maxsnr))))))); + data[20] = data[18]; + data[21] = std::min<uint8_t>(127, uint8_t(0.975 * data012)); double data021 = data[21]; - data[22] = std::min<uint8_t>(127, uint8_t(std::floor((data021 - * (0.98 + (0.02 * std::max<double>(1.0, - (640.0 / fsadc) / maxsnr))))))); - data[23] = data[21]; - data[24] = 0x2e; - data[25] = uint8_t(std::floor(128.0 + std::min<double>(63.0, - 63.0 * (fsadc / 640.0)))); - data[26] = uint8_t(std::floor(std::min<double>(63.0, 63.0 * (fsadc / 640.0) - * (0.92 + (0.08 * (640.0 / fsadc)))))); - data[27] = uint8_t(std::floor(std::min<double>(63.0, - 32.0 * sqrt(fsadc / 640.0)))); - data[28] = uint8_t(std::floor(128.0 + std::min<double>(63.0, - 63.0 * (fsadc / 640.0)))); - data[29] = uint8_t(std::floor(std::min<double>(63.0, - 63.0 * (fsadc / 640.0) - * (0.92 + (0.08 * (640.0 / fsadc)))))); - data[30] = uint8_t(std::floor(std::min<double>(63.0, - 32.0 * sqrt(fsadc / 640.0)))); - data[31] = uint8_t(std::floor(128.0 + std::min<double>(63.0, - 63.0 * (fsadc / 640.0)))); - data[32] = uint8_t(std::floor(std::min<double>(63.0, - 63.0 * (fsadc / 640.0) * (0.92 - + (0.08 * (640.0 / fsadc)))))); - data[33] = uint8_t(std::floor(std::min<double>(63.0, - 63.0 * sqrt(fsadc / 640.0)))); - data[34] = std::min<uint8_t>(127, uint8_t(std::floor(64.0 - * sqrt(fsadc / 640.0)))); + data[22] = std::min<uint8_t>(127, + uint8_t(std::floor( + (data021 + * (0.98 + (0.02 * std::max<double>(1.0, (640.0 / fsadc) / maxsnr))))))); + data[23] = data[21]; + data[24] = 0x2e; + data[25] = + uint8_t(std::floor(128.0 + std::min<double>(63.0, 63.0 * (fsadc / 640.0)))); + data[26] = uint8_t(std::floor(std::min<double>( + 63.0, 63.0 * (fsadc / 640.0) * (0.92 + (0.08 * (640.0 / fsadc)))))); + data[27] = uint8_t(std::floor(std::min<double>(63.0, 32.0 * sqrt(fsadc / 640.0)))); + data[28] = + uint8_t(std::floor(128.0 + std::min<double>(63.0, 63.0 * (fsadc / 640.0)))); + data[29] = uint8_t(std::floor(std::min<double>( + 63.0, 63.0 * (fsadc / 640.0) * (0.92 + (0.08 * (640.0 / fsadc)))))); + data[30] = uint8_t(std::floor(std::min<double>(63.0, 32.0 * sqrt(fsadc / 640.0)))); + data[31] = + uint8_t(std::floor(128.0 + std::min<double>(63.0, 63.0 * (fsadc / 640.0)))); + data[32] = uint8_t(std::floor(std::min<double>( + 63.0, 63.0 * (fsadc / 640.0) * (0.92 + (0.08 * (640.0 / fsadc)))))); + data[33] = uint8_t(std::floor(std::min<double>(63.0, 63.0 * sqrt(fsadc / 640.0)))); + data[34] = std::min<uint8_t>(127, uint8_t(std::floor(64.0 * sqrt(fsadc / 640.0)))); data[35] = 0x40; data[36] = 0x40; data[37] = 0x2c; @@ -708,8 +741,8 @@ void ad9361_device_t::_setup_adc() data[39] = 0x00; /* Program the registers! */ - for(size_t i = 0; i < 40; i++) { - _io_iface->poke8(0x200+i, data[i]); + for (size_t i = 0; i < 40; i++) { + _io_iface->poke8(0x200 + i, data[i]); } } @@ -718,11 +751,12 @@ void ad9361_device_t::_setup_adc() */ void ad9361_device_t::_calibrate_baseband_dc_offset() { - _io_iface->poke8(0x18b, 0x83); //Reset RF DC tracking flag + _io_iface->poke8(0x18b, 0x83); // Reset RF DC tracking flag _io_iface->poke8(0x193, 0x3f); // Calibration settings _io_iface->poke8(0x190, 0x0f); // Set tracking coefficient - //write_ad9361_reg(device, 0x190, /*0x0f*//*0xDF*/0x80*1 | 0x40*1 | (16+8/*+4*/)); // Set tracking coefficient: don't *4 counter, do decim /4, increased gain shift + // write_ad9361_reg(device, 0x190, /*0x0f*//*0xDF*/0x80*1 | 0x40*1 | (16+8/*+4*/)); // + // Set tracking coefficient: don't *4 counter, do decim /4, increased gain shift _io_iface->poke8(0x194, 0x01); // More calibration settings /* Start that calibration, baby. */ @@ -730,7 +764,8 @@ void ad9361_device_t::_calibrate_baseband_dc_offset() _io_iface->poke8(0x016, 0x01); while (_io_iface->peek8(0x016) & 0x01) { if (count > 100) { - throw uhd::runtime_error("[ad9361_device_t] Baseband DC Offset Calibration Failure"); + throw uhd::runtime_error( + "[ad9361_device_t] Baseband DC Offset Calibration Failure"); break; } count++; @@ -763,7 +798,8 @@ void ad9361_device_t::_calibrate_rf_dc_offset() _io_iface->poke8(0x016, 0x02); while (_io_iface->peek8(0x016) & 0x02) { if (count > 200) { - throw uhd::runtime_error("[ad9361_device_t] RF DC Offset Calibration Failure"); + throw uhd::runtime_error( + "[ad9361_device_t] RF DC Offset Calibration Failure"); break; } count++; @@ -814,7 +850,8 @@ void ad9361_device_t::_calibrate_rx_quadrature() _io_iface->poke8(0x016, 0x20); while (_io_iface->peek8(0x016) & 0x20) { if (count > 1000) { - throw uhd::runtime_error("[ad9361_device_t] Rx Quadrature Calibration Failure"); + throw uhd::runtime_error( + "[ad9361_device_t] Rx Quadrature Calibration Failure"); break; } count++; @@ -831,15 +868,15 @@ void ad9361_device_t::_calibrate_rx_quadrature() * The TX quadrature needs to be done twice, once for each TX chain, with * only one register change in between. Thus, this function enacts the * calibrations, and it is called from calibrate_tx_quadrature. */ -void ad9361_device_t::_tx_quadrature_cal_routine() { - +void ad9361_device_t::_tx_quadrature_cal_routine() +{ /* This is a weird process, but here is how it works: * 1) Read the calibrated NCO frequency bits out of 0A3. * 2) Write the two bits to the RX NCO freq part of 0A0. * 3) Re-read 0A3 to get bits [5:0] because maybe they changed? * 4) Update only the TX NCO freq bits in 0A3. * 5) Profit (I hope). */ - uint8_t reg0a3 = _io_iface->peek8(0x0a3); + uint8_t reg0a3 = _io_iface->peek8(0x0a3); uint8_t nco_freq = (reg0a3 & 0xC0); _io_iface->poke8(0x0a0, 0x15 | (nco_freq >> 1)); reg0a3 = _io_iface->peek8(0x0a3); @@ -849,8 +886,8 @@ void ad9361_device_t::_tx_quadrature_cal_routine() { * where the two test tones used for quadrature calibration are outside * of the RX BBF, and therefore don't make it to the ADC. We will check * for that scenario here. */ - double max_cal_freq = (((_baseband_bw * _tfir_factor) - * ((nco_freq >> 6) + 1)) / 32) * 2; + double max_cal_freq = + (((_baseband_bw * _tfir_factor) * ((nco_freq >> 6) + 1)) / 32) * 2; double bbbw = _baseband_bw / 2.0; // bbbw represents the one-sided BW if (bbbw > 28e6) { bbbw = 28e6; @@ -882,7 +919,8 @@ void ad9361_device_t::_tx_quadrature_cal_routine() { _io_iface->poke8(0x016, 0x10); while (_io_iface->peek8(0x016) & 0x10) { if (count > 100) { - throw uhd::runtime_error("[ad9361_device_t] TX Quadrature Calibration Failure"); + throw uhd::runtime_error( + "[ad9361_device_t] TX Quadrature Calibration Failure"); break; } count++; @@ -897,7 +935,8 @@ void ad9361_device_t::_calibrate_tx_quadrature() /* Make sure we are, in fact, in the ALERT state. If not, something is * terribly wrong in the driver execution flow. */ if ((_io_iface->peek8(0x017) & 0x0F) != 5) { - throw uhd::runtime_error("[ad9361_device_t] TX Quad Cal started, but not in ALERT"); + throw uhd::runtime_error( + "[ad9361_device_t] TX Quad Cal started, but not in ALERT"); } /* Turn off free-running and continuous calibrations. Note that this @@ -974,19 +1013,20 @@ void ad9361_device_t::_program_mixer_gm_subtable() /* Program the gain table. * * There are three different gain tables for different frequency ranges! */ -void ad9361_device_t::_program_gain_table() { +void ad9361_device_t::_program_gain_table() +{ /* Figure out which gain table we should be using for our current * frequency band. */ - uint8_t (*gain_table)[3] = NULL; + uint8_t(*gain_table)[3] = NULL; uint8_t new_gain_table; if (_rx_freq < 1300e6) { - gain_table = gain_table_sub_1300mhz; + gain_table = gain_table_sub_1300mhz; new_gain_table = 1; } else if (_rx_freq < 4e9) { - gain_table = gain_table_1300mhz_to_4000mhz; + gain_table = gain_table_1300mhz_to_4000mhz; new_gain_table = 2; } else if (_rx_freq <= 6e9) { - gain_table = gain_table_4000mhz_to_6000mhz; + gain_table = gain_table_4000mhz_to_6000mhz; new_gain_table = 3; } else { new_gain_table = 1; @@ -1112,17 +1152,17 @@ void ad9361_device_t::_setup_synth(direction_t direction, double vcorate) /* Parse the values out of the LUT based on our calculated index... */ uint8_t vco_output_level = synth_cal_lut[vcoindex][0]; - uint8_t vco_varactor = synth_cal_lut[vcoindex][1]; - uint8_t vco_bias_ref = synth_cal_lut[vcoindex][2]; - uint8_t vco_bias_tcf = synth_cal_lut[vcoindex][3]; - uint8_t vco_cal_offset = synth_cal_lut[vcoindex][4]; + uint8_t vco_varactor = synth_cal_lut[vcoindex][1]; + uint8_t vco_bias_ref = synth_cal_lut[vcoindex][2]; + uint8_t vco_bias_tcf = synth_cal_lut[vcoindex][3]; + uint8_t vco_cal_offset = synth_cal_lut[vcoindex][4]; uint8_t vco_varactor_ref = synth_cal_lut[vcoindex][5]; uint8_t charge_pump_curr = synth_cal_lut[vcoindex][6]; - uint8_t loop_filter_c2 = synth_cal_lut[vcoindex][7]; - uint8_t loop_filter_c1 = synth_cal_lut[vcoindex][8]; - uint8_t loop_filter_r1 = synth_cal_lut[vcoindex][9]; - uint8_t loop_filter_c3 = synth_cal_lut[vcoindex][10]; - uint8_t loop_filter_r3 = synth_cal_lut[vcoindex][11]; + uint8_t loop_filter_c2 = synth_cal_lut[vcoindex][7]; + uint8_t loop_filter_c1 = synth_cal_lut[vcoindex][8]; + uint8_t loop_filter_r1 = synth_cal_lut[vcoindex][9]; + uint8_t loop_filter_c3 = synth_cal_lut[vcoindex][10]; + uint8_t loop_filter_r3 = synth_cal_lut[vcoindex][11]; /* ... annnd program! */ if (direction == RX) { @@ -1171,8 +1211,8 @@ double ad9361_device_t::_tune_bbvco(const double rate) _req_coreclk = rate; - const double fref = 40e6; - const int modulus = 2088960; + const double fref = 40e6; + const int modulus = 2088960; const double vcomax = 1430e6; const double vcomin = 672e6; double vcorate; @@ -1181,7 +1221,7 @@ double ad9361_device_t::_tune_bbvco(const double rate) /* Iterate over VCO dividers until appropriate divider is found. */ int i = 1; for (; i <= 6; i++) { - vcodiv = 1 << i; + vcodiv = 1 << i; vcorate = rate * vcodiv; if (vcorate >= vcomin && vcorate <= vcomax) @@ -1196,40 +1236,40 @@ double ad9361_device_t::_tune_bbvco(const double rate) /* Fo = Fref * (Nint + Nfrac / mod) */ int nint = static_cast<int>(vcorate / fref); UHD_LOG_TRACE("AD936X", "[ad9361_device_t::_tune_bbvco] (nint)=" << (vcorate / fref)); - int nfrac = static_cast<int>(boost::math::round(((vcorate / fref) - (double) nint) * (double) modulus)); + int nfrac = static_cast<int>( + boost::math::round(((vcorate / fref) - (double)nint) * (double)modulus)); UHD_LOG_TRACE("AD936X", "[ad9361_device_t::_tune_bbvco] (nfrac)=" << ((vcorate / fref) - (double)nint) * (double)modulus); UHD_LOG_TRACE("AD936X", boost::format("[ad9361_device_t::_tune_bbvco] nint=%d nfrac=%d") % nint % nfrac); - double actual_vcorate = fref - * ((double) nint + ((double) nfrac / (double) modulus)); + double actual_vcorate = fref * ((double)nint + ((double)nfrac / (double)modulus)); /* Scale CP current according to VCO rate */ - const double icp_baseline = 150e-6; + const double icp_baseline = 150e-6; const double freq_baseline = 1280e6; - double icp = icp_baseline * (actual_vcorate / freq_baseline); - int icp_reg = static_cast<int>(icp / 25e-6) - 1; + double icp = icp_baseline * (actual_vcorate / freq_baseline); + int icp_reg = static_cast<int>(icp / 25e-6) - 1; - _io_iface->poke8(0x045, 0x00); // REFCLK / 1 to BBPLL - _io_iface->poke8(0x046, icp_reg & 0x3F); // CP current - _io_iface->poke8(0x048, 0xe8); // BBPLL loop filters - _io_iface->poke8(0x049, 0x5b); // BBPLL loop filters - _io_iface->poke8(0x04a, 0x35); // BBPLL loop filters + _io_iface->poke8(0x045, 0x00); // REFCLK / 1 to BBPLL + _io_iface->poke8(0x046, icp_reg & 0x3F); // CP current + _io_iface->poke8(0x048, 0xe8); // BBPLL loop filters + _io_iface->poke8(0x049, 0x5b); // BBPLL loop filters + _io_iface->poke8(0x04a, 0x35); // BBPLL loop filters _io_iface->poke8(0x04b, 0xe0); - _io_iface->poke8(0x04e, 0x10); // Max accuracy + _io_iface->poke8(0x04e, 0x10); // Max accuracy - _io_iface->poke8(0x043, nfrac & 0xFF); // Nfrac[7:0] - _io_iface->poke8(0x042, (nfrac >> 8) & 0xFF); // Nfrac[15:8] + _io_iface->poke8(0x043, nfrac & 0xFF); // Nfrac[7:0] + _io_iface->poke8(0x042, (nfrac >> 8) & 0xFF); // Nfrac[15:8] _io_iface->poke8(0x041, (nfrac >> 16) & 0xFF); // Nfrac[23:16] - _io_iface->poke8(0x044, nint); // Nint + _io_iface->poke8(0x044, nint); // Nint _calibrate_lock_bbpll(); _regs.bbpll = (_regs.bbpll & 0xF8) | i; - _bbpll_freq = actual_vcorate; + _bbpll_freq = actual_vcorate; _adcclock_freq = (actual_vcorate / vcodiv); return _adcclock_freq; @@ -1242,10 +1282,10 @@ double ad9361_device_t::_tune_bbvco(const double rate) * settings to the appropriate index after a re-tune. */ void ad9361_device_t::_reprogram_gains() { - set_gain(RX, CHAIN_1,_rx1_gain); - set_gain(RX, CHAIN_2,_rx2_gain); - set_gain(TX, CHAIN_1,_tx1_gain); - set_gain(TX, CHAIN_2,_tx2_gain); + set_gain(RX, CHAIN_1, _rx1_gain); + set_gain(RX, CHAIN_2, _rx2_gain); + set_gain(TX, CHAIN_1, _tx1_gain); + set_gain(TX, CHAIN_2, _tx2_gain); } /* This is the internal tune function, not available for a host call. @@ -1255,8 +1295,8 @@ void ad9361_device_t::_reprogram_gains() double ad9361_device_t::_tune_helper(direction_t direction, const double value) { /* The RFPLL runs from 6 GHz - 12 GHz */ - const double fref = 80e6; - const int modulus = 8388593; + const double fref = 80e6; + const int modulus = 8388593; const double vcomax = 12e9; const double vcomin = 6e9; double vcorate; @@ -1265,7 +1305,7 @@ double ad9361_device_t::_tune_helper(direction_t direction, const double value) /* Iterate over VCO dividers until appropriate divider is found. */ int i; for (i = 0; i <= 6; i++) { - vcodiv = 2 << i; + vcodiv = 2 << i; vcorate = value * vcodiv; if (vcorate >= vcomin && vcorate <= vcomax) break; @@ -1273,30 +1313,27 @@ double ad9361_device_t::_tune_helper(direction_t direction, const double value) if (i == 7) throw uhd::runtime_error("[ad9361_device_t] RFVCO can't find valid VCO rate!"); - int nint = static_cast<int>(vcorate / fref); + int nint = static_cast<int>(vcorate / fref); int nfrac = static_cast<int>(((vcorate / fref) - nint) * modulus); - double actual_vcorate = fref * (nint + (double) (nfrac) / modulus); - double actual_lo = actual_vcorate / vcodiv; + double actual_vcorate = fref * (nint + (double)(nfrac) / modulus); + double actual_lo = actual_vcorate / vcodiv; if (direction == RX) { - _req_rx_freq = value; /* Set band-specific settings. */ if (value < _client_params->get_band_edge(AD9361_RX_BAND0)) { _regs.inputsel = (_regs.inputsel & 0xC0) | 0x30; // Port C, balanced - } else if ((value - >= _client_params->get_band_edge(AD9361_RX_BAND0)) - && (value - < _client_params->get_band_edge(AD9361_RX_BAND1))) { + } else if ((value >= _client_params->get_band_edge(AD9361_RX_BAND0)) + && (value < _client_params->get_band_edge(AD9361_RX_BAND1))) { _regs.inputsel = (_regs.inputsel & 0xC0) | 0x0C; // Port B, balanced - } else if ((value - >= _client_params->get_band_edge(AD9361_RX_BAND1)) - && (value <= 6e9)) { + } else if ((value >= _client_params->get_band_edge(AD9361_RX_BAND1)) + && (value <= 6e9)) { _regs.inputsel = (_regs.inputsel & 0xC0) | 0x03; // Port A, balanced } else { - throw uhd::runtime_error("[ad9361_device_t] [_tune_helper] INVALID_CODE_PATH"); + throw uhd::runtime_error( + "[ad9361_device_t] [_tune_helper] INVALID_CODE_PATH"); } _io_iface->poke8(0x004, _regs.inputsel); @@ -1326,18 +1363,17 @@ double ad9361_device_t::_tune_helper(direction_t direction, const double value) return actual_lo; } else { - _req_tx_freq = value; /* Set band-specific settings. */ if (value < _client_params->get_band_edge(AD9361_TX_BAND0)) { _regs.inputsel = _regs.inputsel | 0x40; - } else if ((value - >= _client_params->get_band_edge(AD9361_TX_BAND0)) - && (value <= 6e9)) { + } else if ((value >= _client_params->get_band_edge(AD9361_TX_BAND0)) + && (value <= 6e9)) { _regs.inputsel = _regs.inputsel & 0xBF; } else { - throw uhd::runtime_error("[ad9361_device_t] [_tune_helper] INVALID_CODE_PATH"); + throw uhd::runtime_error( + "[ad9361_device_t] [_tune_helper] INVALID_CODE_PATH"); } _io_iface->poke8(0x004, _regs.inputsel); @@ -1387,8 +1423,8 @@ double ad9361_device_t::_setup_rates(const double rate) * bring-up, and then they will be switched out to reflect the actual * user-requested antenna selections. */ int divfactor = 0; - _tfir_factor = 0; - _rfir_factor = 0; + _tfir_factor = 0; + _rfir_factor = 0; if (rate < 0.33e6) { // RX1 + RX2 enabled, 3, 2, 2, 4 @@ -1397,7 +1433,7 @@ double ad9361_device_t::_setup_rates(const double rate) // TX1 + TX2 enabled, 3, 2, 2, 4 _regs.txfilt = B8(11101111); - divfactor = 48; + divfactor = 48; _tfir_factor = 4; _rfir_factor = 4; } else if (rate < 0.66e6) { @@ -1407,7 +1443,7 @@ double ad9361_device_t::_setup_rates(const double rate) // TX1 + TX2 enabled, 2, 2, 2, 4 _regs.txfilt = B8(11011111); - divfactor = 32; + divfactor = 32; _tfir_factor = 4; _rfir_factor = 4; } else if (rate <= 20e6) { @@ -1417,7 +1453,7 @@ double ad9361_device_t::_setup_rates(const double rate) // TX1 + TX2 enabled, 2, 2, 2, 2 _regs.txfilt = B8(11011110); - divfactor = 16; + divfactor = 16; _tfir_factor = 2; _rfir_factor = 2; } else if ((rate > 20e6) && (rate < 23e6)) { @@ -1427,7 +1463,7 @@ double ad9361_device_t::_setup_rates(const double rate) // TX1 + TX2 enabled, 3, 1, 2, 2 _regs.txfilt = B8(11100110); - divfactor = 24; + divfactor = 24; _tfir_factor = 2; _rfir_factor = 2; } else if ((rate >= 23e6) && (rate < 41e6)) { @@ -1437,7 +1473,7 @@ double ad9361_device_t::_setup_rates(const double rate) // TX1 + TX2 enabled, 1, 2, 2, 2 _regs.txfilt = B8(11001110); - divfactor = 16; + divfactor = 16; _tfir_factor = 2; _rfir_factor = 2; } else if ((rate >= 41e6) && (rate <= 58e6)) { @@ -1447,7 +1483,7 @@ double ad9361_device_t::_setup_rates(const double rate) // TX1 + TX2 enabled, 3, 1, 1, 2 _regs.txfilt = B8(11100010); - divfactor = 12; + divfactor = 12; _tfir_factor = 2; _rfir_factor = 2; } else if ((rate > 58e6) && (rate <= 61.44e6)) { @@ -1458,7 +1494,7 @@ double ad9361_device_t::_setup_rates(const double rate) // TX1 + TX2 enabled, 2, 1, 1, 2 _regs.txfilt = B8(11010010); - divfactor = 8; + divfactor = 8; _tfir_factor = 2; _rfir_factor = 2; } else { @@ -1470,14 +1506,14 @@ double ad9361_device_t::_setup_rates(const double rate) /* Tune the BBPLL to get the ADC and DAC clocks. */ const double adcclk = _tune_bbvco(rate * divfactor); - double dacclk = adcclk; + double dacclk = adcclk; /* The DAC clock must be <= 336e6, and is either the ADC clock or 1/2 the * ADC clock.*/ if (adcclk > 336e6) { /* Make the DAC clock = ADC/2 */ _regs.bbpll = _regs.bbpll | 0x08; - dacclk = adcclk / 2.0; + dacclk = adcclk / 2.0; } else { _regs.bbpll = _regs.bbpll & 0xF7; } @@ -1492,24 +1528,27 @@ double ad9361_device_t::_setup_rates(const double rate) _baseband_bw = (adcclk / divfactor); /* - The Tx & Rx FIR calculate 16 taps per clock cycle. This limits the number of available taps to the ratio of DAC_CLK/ADC_CLK - to the input data rate multiplied by 16. For example, if the input data rate is 25 MHz and DAC_CLK is 100 MHz, - then the ratio of DAC_CLK to the input data rate is 100/25 or 4. In this scenario, the total number of taps available is 64. - - Also, whilst the Rx FIR filter always has memory available for 128 taps, the Tx FIR Filter can only support a maximum length of 64 taps - in 1x interpolation mode, and 128 taps in 2x & 4x modes. + The Tx & Rx FIR calculate 16 taps per clock cycle. This limits the number of + available taps to the ratio of DAC_CLK/ADC_CLK to the input data rate multiplied + by 16. For example, if the input data rate is 25 MHz and DAC_CLK is 100 MHz, then the + ratio of DAC_CLK to the input data rate is 100/25 or 4. In this scenario, the total + number of taps available is 64. + + Also, whilst the Rx FIR filter always has memory available for 128 taps, the Tx FIR + Filter can only support a maximum length of 64 taps in 1x interpolation mode, and 128 + taps in 2x & 4x modes. */ - const size_t max_tx_taps = std::min<size_t>( - std::min<size_t>((16 * (int)((dacclk / rate) + 0.5)), 128), + const size_t max_tx_taps = + std::min<size_t>(std::min<size_t>((16 * (int)((dacclk / rate) + 0.5)), 128), (_tfir_factor == 1) ? 64 : 128); - const size_t max_rx_taps = std::min<size_t>((16 * (size_t)((adcclk / rate) + 0.5)), - 128); + const size_t max_rx_taps = + std::min<size_t>((16 * (size_t)((adcclk / rate) + 0.5)), 128); const size_t num_tx_taps = get_num_taps(max_tx_taps); const size_t num_rx_taps = get_num_taps(max_rx_taps); - _setup_tx_fir(num_tx_taps,_tfir_factor); - _setup_rx_fir(num_rx_taps,_rfir_factor); + _setup_tx_fir(num_tx_taps, _tfir_factor); + _setup_rx_fir(num_rx_taps, _rfir_factor); return _baseband_bw; } @@ -1522,42 +1561,42 @@ void ad9361_device_t::initialize() std::lock_guard<std::recursive_mutex> lock(_mutex); /* Initialize shadow registers. */ - _regs.vcodivs = 0x00; - _regs.inputsel = 0x30; - _regs.rxfilt = 0x00; - _regs.txfilt = 0x00; - _regs.bbpll = 0x02; + _regs.vcodivs = 0x00; + _regs.inputsel = 0x30; + _regs.rxfilt = 0x00; + _regs.txfilt = 0x00; + _regs.bbpll = 0x02; _regs.bbftune_config = 0x1e; - _regs.bbftune_mode = 0x1e; + _regs.bbftune_mode = 0x1e; /* Initialize private VRQ fields. */ - _rx_freq = DEFAULT_RX_FREQ; - _tx_freq = DEFAULT_TX_FREQ; - _req_rx_freq = 0.0; - _req_tx_freq = 0.0; - _baseband_bw = 0.0; - _req_clock_rate = 0.0; - _req_coreclk = 0.0; - _bbpll_freq = 0.0; - _adcclock_freq = 0.0; - _rx_bbf_tunediv = 0; - _curr_gain_table = 0; - _rx1_gain = 0; - _rx2_gain = 0; - _tx1_gain = 0; - _tx2_gain = 0; - _use_dc_offset_tracking = true; + _rx_freq = DEFAULT_RX_FREQ; + _tx_freq = DEFAULT_TX_FREQ; + _req_rx_freq = 0.0; + _req_tx_freq = 0.0; + _baseband_bw = 0.0; + _req_clock_rate = 0.0; + _req_coreclk = 0.0; + _bbpll_freq = 0.0; + _adcclock_freq = 0.0; + _rx_bbf_tunediv = 0; + _curr_gain_table = 0; + _rx1_gain = 0; + _rx2_gain = 0; + _tx1_gain = 0; + _tx2_gain = 0; + _use_dc_offset_tracking = true; _use_iq_balance_tracking = true; - _rx1_agc_mode = GAIN_MODE_SLOW_AGC; - _rx2_agc_mode = GAIN_MODE_SLOW_AGC; - _rx1_agc_enable = false; - _rx2_agc_enable = false; - _rx_analog_bw = 0; - _tx_analog_bw = 0; - _rx_tia_lp_bw = 0; - _tx_sec_lp_bw = 0; - _rx_bb_lp_bw = 0; - _tx_bb_lp_bw = 0; + _rx1_agc_mode = GAIN_MODE_SLOW_AGC; + _rx2_agc_mode = GAIN_MODE_SLOW_AGC; + _rx1_agc_enable = false; + _rx2_agc_enable = false; + _rx_analog_bw = 0; + _tx_analog_bw = 0; + _rx_tia_lp_bw = 0; + _tx_sec_lp_bw = 0; + _rx_bb_lp_bw = 0; + _tx_bb_lp_bw = 0; /* Reset the device. */ _io_iface->poke8(0x000, 0x01); @@ -1567,7 +1606,10 @@ void ad9361_device_t::initialize() /* Check device ID to make sure iface works */ uint32_t device_id = (_io_iface->peek8(0x037) & 0x8); if (device_id != 0x8) { - throw uhd::runtime_error(str(boost::format("[ad9361_device_t::initialize] Device ID readback failure. Expected: 0x8, Received: 0x%x") % device_id)); + throw uhd::runtime_error( + str(boost::format("[ad9361_device_t::initialize] Device ID readback failure. " + "Expected: 0x8, Received: 0x%x") + % device_id)); } /* There is not a WAT big enough for this. */ @@ -1582,20 +1624,20 @@ void ad9361_device_t::initialize() /* Enable clocks. */ switch (_client_params->get_clocking_mode()) { - case clocking_mode_t::AD9361_XTAL_N_CLK_PATH: { - _io_iface->poke8(0x009, 0x17); - } break; - - case clocking_mode_t::AD9361_XTAL_P_CLK_PATH: { - _io_iface->poke8(0x009, 0x07); - _io_iface->poke8(0x292, 0x08); - _io_iface->poke8(0x293, 0x80); - _io_iface->poke8(0x294, 0x00); - _io_iface->poke8(0x295, 0x14); - } break; + case clocking_mode_t::AD9361_XTAL_N_CLK_PATH: { + _io_iface->poke8(0x009, 0x17); + } break; + + case clocking_mode_t::AD9361_XTAL_P_CLK_PATH: { + _io_iface->poke8(0x009, 0x07); + _io_iface->poke8(0x292, 0x08); + _io_iface->poke8(0x293, 0x80); + _io_iface->poke8(0x294, 0x00); + _io_iface->poke8(0x295, 0x14); + } break; - default: - throw uhd::runtime_error("[ad9361_device_t] NOT IMPLEMENTED"); + default: + throw uhd::runtime_error("[ad9361_device_t] NOT IMPLEMENTED"); } std::this_thread::sleep_for(std::chrono::milliseconds(20)); @@ -1606,34 +1648,33 @@ void ad9361_device_t::initialize() * FDD dual port DDR CMOS no swap. * Force TX on one port, RX on the other. */ switch (_client_params->get_digital_interface_mode()) { - case AD9361_DDR_FDD_LVCMOS: { - _io_iface->poke8(0x010, 0xc8); // Swap I&Q on Tx, Swap I&Q on Rx, Toggle frame sync mode - _io_iface->poke8(0x011, 0x00); - _io_iface->poke8(0x012, 0x02); - } break; + case AD9361_DDR_FDD_LVCMOS: { + _io_iface->poke8( + 0x010, 0xc8); // Swap I&Q on Tx, Swap I&Q on Rx, Toggle frame sync mode + _io_iface->poke8(0x011, 0x00); + _io_iface->poke8(0x012, 0x02); + } break; - case AD9361_DDR_FDD_LVDS: { - _io_iface->poke8(0x010, 0xcc); // Swap I&Q on Tx, Swap I&Q on Rx, Toggle frame sync mode, 2R2T timing. - _io_iface->poke8(0x011, 0x00); - _io_iface->poke8(0x012, 0x10); + case AD9361_DDR_FDD_LVDS: { + _io_iface->poke8(0x010, 0xcc); // Swap I&Q on Tx, Swap I&Q on Rx, Toggle frame + // sync mode, 2R2T timing. + _io_iface->poke8(0x011, 0x00); + _io_iface->poke8(0x012, 0x10); - //LVDS Specific - _io_iface->poke8(0x03C, 0x23); - _io_iface->poke8(0x03D, 0xFF); - _io_iface->poke8(0x03E, 0x0F); - } break; + // LVDS Specific + _io_iface->poke8(0x03C, 0x23); + _io_iface->poke8(0x03D, 0xFF); + _io_iface->poke8(0x03E, 0x0F); + } break; - default: - throw uhd::runtime_error("[ad9361_device_t] NOT IMPLEMENTED"); + default: + throw uhd::runtime_error("[ad9361_device_t] NOT IMPLEMENTED"); } /* Data delay for TX and RX data clocks */ - digital_interface_delays_t timing = - _client_params->get_digital_interface_timing(); - uint8_t rx_delays = ((timing.rx_clk_delay & 0xF) << 4) - | (timing.rx_data_delay & 0xF); - uint8_t tx_delays = ((timing.tx_clk_delay & 0xF) << 4) - | (timing.tx_data_delay & 0xF); + digital_interface_delays_t timing = _client_params->get_digital_interface_timing(); + uint8_t rx_delays = ((timing.rx_clk_delay & 0xF) << 4) | (timing.rx_data_delay & 0xF); + uint8_t tx_delays = ((timing.tx_clk_delay & 0xF) << 4) | (timing.tx_data_delay & 0xF); _io_iface->poke8(0x006, rx_delays); _io_iface->poke8(0x007, tx_delays); @@ -1670,7 +1711,7 @@ void ad9361_device_t::initialize() _io_iface->poke8(0x036, 0xFF); /* Setup GPO */ - _io_iface->poke8(0x03a, 0x27); //set delay register + _io_iface->poke8(0x03a, 0x27); // set delay register _io_iface->poke8(0x020, 0x00); // GPO Auto Enable Setup in RX and TX _io_iface->poke8(0x027, 0x03); // GPO Manual and GPO auto value in ALERT _io_iface->poke8(0x028, 0x00); // GPO_0 RX Delay @@ -1739,16 +1780,16 @@ void ad9361_device_t::initialize() // cals done, set PPORT config switch (_client_params->get_digital_interface_mode()) { - case AD9361_DDR_FDD_LVCMOS: { - _io_iface->poke8(0x012, 0x02); - } break; + case AD9361_DDR_FDD_LVCMOS: { + _io_iface->poke8(0x012, 0x02); + } break; - case AD9361_DDR_FDD_LVDS: { - _io_iface->poke8(0x012, 0x10); - } break; + case AD9361_DDR_FDD_LVDS: { + _io_iface->poke8(0x012, 0x10); + } break; - default: - throw uhd::runtime_error("[ad9361_device_t] NOT IMPLEMENTED"); + default: + throw uhd::runtime_error("[ad9361_device_t] NOT IMPLEMENTED"); } _io_iface->poke8(0x013, 0x01); // Set ENSM FDD bit @@ -1794,7 +1835,8 @@ double ad9361_device_t::set_clock_rate(const double req_rate) std::lock_guard<std::recursive_mutex> lock(_mutex); if (req_rate > 61.44e6) { - throw uhd::runtime_error("[ad9361_device_t] Requested master clock rate outside range"); + throw uhd::runtime_error( + "[ad9361_device_t] Requested master clock rate outside range"); } UHD_LOG_TRACE("AD936X", "[ad9361_device_t::set_clock_rate] req_rate=" << req_rate); @@ -1812,21 +1854,22 @@ double ad9361_device_t::set_clock_rate(const double req_rate) * there, transition the ENSM to State 0. */ uint8_t current_state = _io_iface->peek8(0x017) & 0x0F; switch (current_state) { - case 0x05: - /* We are in the ALERT state. */ - _io_iface->poke8(0x014, 0x21); - std::this_thread::sleep_for(std::chrono::milliseconds(5)); - _io_iface->poke8(0x014, 0x00); - break; + case 0x05: + /* We are in the ALERT state. */ + _io_iface->poke8(0x014, 0x21); + std::this_thread::sleep_for(std::chrono::milliseconds(5)); + _io_iface->poke8(0x014, 0x00); + break; - case 0x0A: - /* We are in the FDD state. */ - _io_iface->poke8(0x014, 0x00); - break; + case 0x0A: + /* We are in the FDD state. */ + _io_iface->poke8(0x014, 0x00); + break; - default: - throw uhd::runtime_error("[ad9361_device_t] [set_clock_rate:1] AD9361 in unknown state"); - break; + default: + throw uhd::runtime_error( + "[ad9361_device_t] [set_clock_rate:1] AD9361 in unknown state"); + break; }; /* Store the current chain / antenna selections so that we can restore @@ -1842,9 +1885,9 @@ double ad9361_device_t::set_clock_rate(const double req_rate) UHD_LOG_TRACE("AD936X", "[ad9361_device_t::set_clock_rate] rate=" << rate); /* Transition to the ALERT state and calibrate everything. */ - _io_iface->poke8(0x015, 0x04); //dual synth mode, synth en ctrl en - _io_iface->poke8(0x014, 0x05); //use SPI for TXNRX ctrl, to ALERT, TX on - _io_iface->poke8(0x013, 0x01); //enable ENSM + _io_iface->poke8(0x015, 0x04); // dual synth mode, synth en ctrl en + _io_iface->poke8(0x014, 0x05); // use SPI for TXNRX ctrl, to ALERT, TX on + _io_iface->poke8(0x013, 0x01); // enable ENSM std::this_thread::sleep_for(std::chrono::milliseconds(1)); _calibrate_synth_charge_pumps(); @@ -1882,38 +1925,39 @@ double ad9361_device_t::set_clock_rate(const double req_rate) switch (_client_params->get_digital_interface_mode()) { case AD9361_DDR_FDD_LVCMOS: { _io_iface->poke8(0x012, 0x02); - }break; + } break; case AD9361_DDR_FDD_LVDS: { _io_iface->poke8(0x012, 0x10); - }break; + } break; default: - throw uhd::runtime_error("[ad9361_device_t] NOT IMPLEMENTED"); + throw uhd::runtime_error("[ad9361_device_t] NOT IMPLEMENTED"); } _io_iface->poke8(0x013, 0x01); // Set ENSM FDD bit _io_iface->poke8(0x015, 0x04); // dual synth mode, synth en ctrl en /* End the function in the same state as the entry state. */ switch (current_state) { - case 0x05: - /* We are already in ALERT. */ - break; - - case 0x0A: - /* Transition back to FDD, and restore the original antenna - * / chain selections. */ - _regs.txfilt = (_regs.txfilt & 0x3F) | orig_tx_chains; - _regs.rxfilt = (_regs.rxfilt & 0x3F) | orig_rx_chains; - - _io_iface->poke8(0x002, _regs.txfilt); - _io_iface->poke8(0x003, _regs.rxfilt); - _io_iface->poke8(0x014, 0x21); - break; + case 0x05: + /* We are already in ALERT. */ + break; - default: - throw uhd::runtime_error("[ad9361_device_t] [set_clock_rate:2] AD9361 in unknown state"); - break; + case 0x0A: + /* Transition back to FDD, and restore the original antenna + * / chain selections. */ + _regs.txfilt = (_regs.txfilt & 0x3F) | orig_tx_chains; + _regs.rxfilt = (_regs.rxfilt & 0x3F) | orig_rx_chains; + + _io_iface->poke8(0x002, _regs.txfilt); + _io_iface->poke8(0x003, _regs.rxfilt); + _io_iface->poke8(0x014, 0x21); + break; + + default: + throw uhd::runtime_error( + "[ad9361_device_t] [set_clock_rate:2] AD9361 in unknown state"); + break; }; return get_clock_rate(); @@ -1967,9 +2011,9 @@ void ad9361_device_t::set_active_chains(bool tx1, bool tx2, bool rx1, bool rx2) /* Check for FDD state */ uint8_t set_back_to_fdd = 0; - uint8_t ensm_state = _io_iface->peek8(0x017) & 0x0F; - if (ensm_state == 0xA) // FDD - { + uint8_t ensm_state = _io_iface->peek8(0x017) & 0x0F; + if (ensm_state == 0xA) // FDD + { /* Put into ALERT state (via the FDD flush state). */ _io_iface->poke8(0x014, 0x01); set_back_to_fdd = 1; @@ -2003,38 +2047,42 @@ void ad9361_device_t::set_active_chains(bool tx1, bool tx2, bool rx1, bool rx2) void ad9361_device_t::set_timing_mode(const ad9361_device_t::timing_mode_t timing_mode) { switch (_client_params->get_digital_interface_mode()) { - case AD9361_DDR_FDD_LVCMOS: { - switch(timing_mode) { - case TIMING_MODE_1R1T: { - _io_iface->poke8(0x010, 0xc8); // Swap I&Q on Tx, Swap I&Q on Rx, Toggle frame sync mode - break; - } - case TIMING_MODE_2R2T: { - throw uhd::runtime_error("[ad9361_device_t] [set_timing_mode] 2R2T timing mode not supported for CMOS"); - break; - } - default: - UHD_THROW_INVALID_CODE_PATH(); - } - break; - } - case AD9361_DDR_FDD_LVDS: { - switch(timing_mode) { - case TIMING_MODE_1R1T: { - _io_iface->poke8(0x010, 0xc8); // Swap I&Q on Tx, Swap I&Q on Rx, Toggle frame sync mode, 1R1T timing. + case AD9361_DDR_FDD_LVCMOS: { + switch (timing_mode) { + case TIMING_MODE_1R1T: { + _io_iface->poke8(0x010, + 0xc8); // Swap I&Q on Tx, Swap I&Q on Rx, Toggle frame sync mode + break; + } + case TIMING_MODE_2R2T: { + throw uhd::runtime_error("[ad9361_device_t] [set_timing_mode] 2R2T " + "timing mode not supported for CMOS"); + break; + } + default: + UHD_THROW_INVALID_CODE_PATH(); + } break; } - case TIMING_MODE_2R2T: { - _io_iface->poke8(0x010, 0xcc); // Swap I&Q on Tx, Swap I&Q on Rx, Toggle frame sync mode, 2R2T timing. + case AD9361_DDR_FDD_LVDS: { + switch (timing_mode) { + case TIMING_MODE_1R1T: { + _io_iface->poke8(0x010, 0xc8); // Swap I&Q on Tx, Swap I&Q on Rx, + // Toggle frame sync mode, 1R1T timing. + break; + } + case TIMING_MODE_2R2T: { + _io_iface->poke8(0x010, 0xcc); // Swap I&Q on Tx, Swap I&Q on Rx, + // Toggle frame sync mode, 2R2T timing. + break; + } + default: + UHD_THROW_INVALID_CODE_PATH(); + } break; } default: - UHD_THROW_INVALID_CODE_PATH(); - } - break; - } - default: - throw uhd::runtime_error("[ad9361_device_t] NOT IMPLEMENTED"); + throw uhd::runtime_error("[ad9361_device_t] NOT IMPLEMENTED"); } } @@ -2138,7 +2186,6 @@ double ad9361_device_t::set_gain(direction_t direction, chain_t chain, const dou std::lock_guard<std::recursive_mutex> lock(_mutex); if (direction == RX) { - int gain_index = static_cast<int>(value); /* Clip the gain values to the proper min/max gain values. */ @@ -2169,7 +2216,7 @@ double ad9361_device_t::set_gain(direction_t direction, chain_t chain, const dou * "value" is out of bounds, so range checking must be performed * outside this function. */ - double atten = AD9361_MAX_GAIN - value; + double atten = AD9361_MAX_GAIN - value; uint32_t attenreg = uint32_t(atten * 4); if (chain == CHAIN_1) { _tx1_gain = value; @@ -2180,11 +2227,11 @@ double ad9361_device_t::set_gain(direction_t direction, chain_t chain, const dou _io_iface->poke8(0x075, attenreg & 0xFF); _io_iface->poke8(0x076, (attenreg >> 8) & 0x01); } - return AD9361_MAX_GAIN - ((double) (attenreg) / 4); + return AD9361_MAX_GAIN - ((double)(attenreg) / 4); } } -void ad9361_device_t::output_test_tone() // On RF side! +void ad9361_device_t::output_test_tone() // On RF side! { std::lock_guard<std::recursive_mutex> lock(_mutex); /* Output a 480 kHz tone at 800 MHz */ @@ -2212,19 +2259,20 @@ void ad9361_device_t::data_port_loopback(const bool loopback_enabled) * -0.25dB / bit 9bit resolution.*/ double ad9361_device_t::get_rssi(chain_t chain) { - uint32_t reg_rssi = 0; + uint32_t reg_rssi = 0; uint8_t lsb_bit_pos = 0; if (chain == CHAIN_1) { - reg_rssi = 0x1A7; + reg_rssi = 0x1A7; lsb_bit_pos = 0; - }else { - reg_rssi = 0x1A9; + } else { + reg_rssi = 0x1A9; lsb_bit_pos = 1; } uint8_t msbs = _io_iface->peek8(reg_rssi); - uint8_t lsb = ((_io_iface->peek8(0x1AB)) >> lsb_bit_pos) & 0x01; + uint8_t lsb = ((_io_iface->peek8(0x1AB)) >> lsb_bit_pos) & 0x01; uint16_t val = ((msbs << 1) | lsb); - double rssi = (-0.25f * ((double)val)); //-0.25dB/lsb (See Gain Control Users Guide p. 25) + double rssi = + (-0.25f * ((double)val)); //-0.25dB/lsb (See Gain Control Users Guide p. 25) return rssi; } @@ -2235,39 +2283,40 @@ double ad9361_device_t::get_rssi(chain_t chain) */ double ad9361_device_t::_get_temperature(const double cal_offset, const double timeout) { - //set 0x01D[0] to 1 to disable AuxADC GPIO reading + // set 0x01D[0] to 1 to disable AuxADC GPIO reading uint8_t tmp = 0; - tmp = _io_iface->peek8(0x01D); + tmp = _io_iface->peek8(0x01D); _io_iface->poke8(0x01D, (tmp | 0x01)); - _io_iface->poke8(0x00B, 0); //set offset to 0 - - _io_iface->poke8(0x00C, 0x01); //start reading, clears bit 0x00C[1] - auto end_time = - std::chrono::steady_clock::now() - + std::chrono::milliseconds(int64_t(timeout * 1000)); - //wait for valid data (toggle of bit 1 in 0x00C) - while(((_io_iface->peek8(0x00C) >> 1) & 0x01) == 0) { + _io_iface->poke8(0x00B, 0); // set offset to 0 + + _io_iface->poke8(0x00C, 0x01); // start reading, clears bit 0x00C[1] + auto end_time = std::chrono::steady_clock::now() + + std::chrono::milliseconds(int64_t(timeout * 1000)); + // wait for valid data (toggle of bit 1 in 0x00C) + while (((_io_iface->peek8(0x00C) >> 1) & 0x01) == 0) { std::this_thread::sleep_for(std::chrono::microseconds(100)); if (std::chrono::steady_clock::now() > end_time) { throw uhd::runtime_error( "[ad9361_device_t] timeout while reading temperature"); } } - _io_iface->poke8(0x00C, 0x00); //clear read flag + _io_iface->poke8(0x00C, 0x00); // clear read flag - uint8_t temp = _io_iface->peek8(0x00E); //read temperature. - double tmp_temp = temp/1.140f; //according to ADI driver - tmp_temp = tmp_temp + cal_offset; //Constant offset acquired by one point calibration. + uint8_t temp = _io_iface->peek8(0x00E); // read temperature. + double tmp_temp = temp / 1.140f; // according to ADI driver + tmp_temp = tmp_temp + cal_offset; // Constant offset acquired by one point + // calibration. return tmp_temp; } -double ad9361_device_t::get_average_temperature(const double cal_offset, const size_t num_samples) +double ad9361_device_t::get_average_temperature( + const double cal_offset, const size_t num_samples) { double d_temp = 0; - for(size_t i = 0; i < num_samples; i++) { + for (size_t i = 0; i < num_samples; i++) { double tmp_temp = _get_temperature(cal_offset); - d_temp += (tmp_temp/num_samples); + d_temp += (tmp_temp / num_samples); } return d_temp; } @@ -2289,7 +2338,8 @@ void ad9361_device_t::set_dc_offset_auto(direction_t direction, const bool on) _use_dc_offset_tracking = on; _configure_bb_dc_tracking(); } else { - throw uhd::runtime_error("[ad9361_device_t] [set_dc_offset_auto] Tx DC tracking not supported"); + throw uhd::runtime_error( + "[ad9361_device_t] [set_dc_offset_auto] Tx DC tracking not supported"); } } @@ -2312,7 +2362,8 @@ void ad9361_device_t::set_iq_balance_auto(direction_t direction, const bool on) _io_iface->poke8(0x014, 0x21); // FDD mode } } else { - throw uhd::runtime_error("[ad9361_device_t] [set_iq_balance_auto] Tx IQ tracking not supported"); + throw uhd::runtime_error( + "[ad9361_device_t] [set_iq_balance_auto] Tx IQ tracking not supported"); } } @@ -2321,41 +2372,41 @@ void ad9361_device_t::set_iq_balance_auto(direction_t direction, const bool on) * the gain configuration will be reloaded. */ void ad9361_device_t::_setup_agc(chain_t chain, gain_mode_t gain_mode) { - uint8_t gain_mode_reg = 0; - uint8_t gain_mode_prev = 0; + uint8_t gain_mode_reg = 0; + uint8_t gain_mode_prev = 0; uint8_t gain_mode_bits_pos = 0; - gain_mode_reg = _io_iface->peek8(0x0FA); + gain_mode_reg = _io_iface->peek8(0x0FA); gain_mode_prev = (gain_mode_reg & 0x0F); if (chain == CHAIN_1) { gain_mode_bits_pos = 0; } else if (chain == CHAIN_2) { gain_mode_bits_pos = 2; - } else - { + } else { throw uhd::runtime_error("[ad9361_device_t] Wrong value for chain"); } - gain_mode_reg = (gain_mode_reg & (~(0x03<<gain_mode_bits_pos))); //clear mode bits + gain_mode_reg = (gain_mode_reg & (~(0x03 << gain_mode_bits_pos))); // clear mode bits switch (gain_mode) { case GAIN_MODE_MANUAL: - //leave bits cleared + // leave bits cleared break; case GAIN_MODE_SLOW_AGC: - gain_mode_reg = (gain_mode_reg | (0x02<<gain_mode_bits_pos)); + gain_mode_reg = (gain_mode_reg | (0x02 << gain_mode_bits_pos)); break; case GAIN_MODE_FAST_AGC: - gain_mode_reg = (gain_mode_reg | (0x01<<gain_mode_bits_pos)); + gain_mode_reg = (gain_mode_reg | (0x01 << gain_mode_bits_pos)); break; default: throw uhd::runtime_error("[ad9361_device_t] Gain mode does not exist"); } _io_iface->poke8(0x0FA, gain_mode_reg); uint8_t gain_mode_status = _io_iface->peek8(0x0FA); - gain_mode_status = (gain_mode_status & 0x0F); + gain_mode_status = (gain_mode_status & 0x0F); /*Check if gain mode configuration needs to be reprogrammed*/ - if (((gain_mode_prev == 0) && (gain_mode_status != 0)) || ((gain_mode_prev != 0) && (gain_mode_status == 0))) { + if (((gain_mode_prev == 0) && (gain_mode_status != 0)) + || ((gain_mode_prev != 0) && (gain_mode_status == 0))) { if (gain_mode_status == 0) { /*load manual mode config*/ _setup_gain_control(false); @@ -2368,50 +2419,45 @@ void ad9361_device_t::_setup_agc(chain_t chain, gain_mode_t gain_mode) void ad9361_device_t::set_agc(chain_t chain, bool enable) { - if(chain == CHAIN_1) { + if (chain == CHAIN_1) { _rx1_agc_enable = enable; - if(enable) { + if (enable) { _setup_agc(chain, _rx1_agc_mode); } else { _setup_agc(chain, GAIN_MODE_MANUAL); } - } else if (chain == CHAIN_2){ + } else if (chain == CHAIN_2) { _rx2_agc_enable = enable; - if(enable) { + if (enable) { _setup_agc(chain, _rx2_agc_mode); } else { _setup_agc(chain, GAIN_MODE_MANUAL); } - } else - { + } else { throw uhd::runtime_error("[ad9361_device_t] Wrong value for chain"); } } void ad9361_device_t::set_agc_mode(chain_t chain, gain_mode_t gain_mode) { - if(chain == CHAIN_1) { + if (chain == CHAIN_1) { _rx1_agc_mode = gain_mode; - if(_rx1_agc_enable) { + if (_rx1_agc_enable) { _setup_agc(chain, _rx1_agc_mode); } - } else if(chain == CHAIN_2){ + } else if (chain == CHAIN_2) { _rx2_agc_mode = gain_mode; - if(_rx2_agc_enable) { + if (_rx2_agc_enable) { _setup_agc(chain, _rx2_agc_mode); } - } else - { + } else { throw uhd::runtime_error("[ad9361_device_t] Wrong value for chain"); } } std::vector<std::string> ad9361_device_t::get_filter_names(direction_t direction) { - auto& filters = (direction == RX) - ? _rx_filters - : _tx_filters - ; + auto& filters = (direction == RX) ? _rx_filters : _tx_filters; std::vector<std::string> ret; ret.reserve(filters.size()); @@ -2423,68 +2469,53 @@ std::vector<std::string> ad9361_device_t::get_filter_names(direction_t direction } filter_info_base::sptr ad9361_device_t::get_filter( - direction_t direction, - chain_t chain, - const std::string &name -) { - auto& filters = (direction == RX) - ? _rx_filters - : _tx_filters - ; + direction_t direction, chain_t chain, const std::string& name) +{ + auto& filters = (direction == RX) ? _rx_filters : _tx_filters; if (!filters.count(name)) { throw uhd::runtime_error( - "ad9361_device_t::get_filter this filter does not exist: " + name - ); + "ad9361_device_t::get_filter this filter does not exist: " + name); } // Check entry 0 in the tuple (the getter) exists before calling it if (!std::get<0>(filters[name])) { throw uhd::runtime_error( - "ad9361_device_t::get_filter this filter can not be read: " + name - ); + "ad9361_device_t::get_filter this filter can not be read: " + name); } return std::get<0>(filters[name])(chain); } -void ad9361_device_t::set_filter( - direction_t direction, - chain_t chain, - const std::string &name, - filter_info_base::sptr filter -) { - auto& filters = (direction == RX) - ? _rx_filters - : _tx_filters - ; +void ad9361_device_t::set_filter(direction_t direction, + chain_t chain, + const std::string& name, + filter_info_base::sptr filter) +{ + auto& filters = (direction == RX) ? _rx_filters : _tx_filters; if (!filters.count(name)) { throw uhd::runtime_error( - "ad9361_device_t::set_filter this filter does not exist: " + name - ); + "ad9361_device_t::set_filter this filter does not exist: " + name); } // Check entry 1 in the tuple (the setter) exists before calling it if (!std::get<1>(filters[name])) { throw uhd::runtime_error( - "ad9361_device_t::set_filter this filter can not be written: " + - name - ); + "ad9361_device_t::set_filter this filter can not be written: " + name); } std::get<1>(filters[name])(chain, filter); } double ad9361_device_t::set_bw_filter(direction_t direction, const double rf_bw) { - //both low pass filters are programmed to the same bw. However, their cutoffs will differ. - //Together they should create the requested bb bw. - //Select rf_bw if it is between AD9361_MIN_BW & AD9361_MAX_BW. + // both low pass filters are programmed to the same bw. However, their cutoffs will + // differ. Together they should create the requested bb bw. Select rf_bw if it is + // between AD9361_MIN_BW & AD9361_MAX_BW. const double clipped_bw = std::min(std::max(rf_bw, AD9361_MIN_BW), AD9361_MAX_BW); - if(direction == RX) - { - _rx_bb_lp_bw = _calibrate_baseband_rx_analog_filter(clipped_bw); //returns bb bw + if (direction == RX) { + _rx_bb_lp_bw = _calibrate_baseband_rx_analog_filter(clipped_bw); // returns bb bw _rx_tia_lp_bw = _calibrate_rx_TIAs(clipped_bw); _rx_analog_bw = clipped_bw; } else { - _tx_bb_lp_bw = _calibrate_baseband_tx_analog_filter(clipped_bw); //returns bb bw + _tx_bb_lp_bw = _calibrate_baseband_tx_analog_filter(clipped_bw); // returns bb bw _tx_sec_lp_bw = _calibrate_secondary_tx_filter(clipped_bw); _tx_analog_bw = clipped_bw; } @@ -2492,20 +2523,20 @@ double ad9361_device_t::set_bw_filter(direction_t direction, const double rf_bw) return (clipped_bw); } -void ad9361_device_t::_set_fir_taps(direction_t direction, chain_t chain, const std::vector<int16_t>& taps) +void ad9361_device_t::_set_fir_taps( + direction_t direction, chain_t chain, const std::vector<int16_t>& taps) { - size_t num_taps = taps.size(); + size_t num_taps = taps.size(); size_t num_taps_avail = _get_num_fir_taps(direction); - if(num_taps == num_taps_avail) - { + if (num_taps == num_taps_avail) { boost::scoped_array<uint16_t> coeffs(new uint16_t[num_taps_avail]); - for (size_t i = 0; i < num_taps_avail; i++) - { + for (size_t i = 0; i < num_taps_avail; i++) { coeffs[i] = uint16_t(taps[i]); } _program_fir_filter(direction, chain, num_taps_avail, coeffs.get()); - } else if(num_taps < num_taps_avail){ - throw uhd::runtime_error("ad9361_device_t::_set_fir_taps not enough coefficients."); + } else if (num_taps < num_taps_avail) { + throw uhd::runtime_error( + "ad9361_device_t::_set_fir_taps not enough coefficients."); } else { throw uhd::runtime_error("ad9361_device_t::_set_fir_taps too many coefficients."); } @@ -2514,7 +2545,7 @@ void ad9361_device_t::_set_fir_taps(direction_t direction, chain_t chain, const size_t ad9361_device_t::_get_num_fir_taps(direction_t direction) { uint8_t num = 0; - if(direction == RX) + if (direction == RX) num = _io_iface->peek8(0x0F5); else num = _io_iface->peek8(0x065); @@ -2525,7 +2556,7 @@ size_t ad9361_device_t::_get_num_fir_taps(direction_t direction) size_t ad9361_device_t::_get_fir_dec_int(direction_t direction) { uint8_t dec_int = 0; - if(direction == RX) + if (direction == RX) dec_int = _io_iface->peek8(0x003); else dec_int = _io_iface->peek8(0x002); @@ -2535,8 +2566,7 @@ size_t ad9361_device_t::_get_fir_dec_int(direction_t direction) * 2 = dec/int by 2 * 3 = dec/int by 4 */ dec_int = (dec_int & 0x03); - if(dec_int == 3) - { + if (dec_int == 3) { return 4; } return dec_int; @@ -2548,41 +2578,39 @@ std::vector<int16_t> ad9361_device_t::_get_fir_taps(direction_t direction, chain size_t num_taps = _get_num_fir_taps(direction); uint8_t config; uint8_t reg_numtaps = (((num_taps / 16) - 1) & 0x07) << 5; - config = reg_numtaps | 0x02; //start the programming clock + config = reg_numtaps | 0x02; // start the programming clock - if(chain == CHAIN_1) - { + if (chain == CHAIN_1) { config = config | (1 << 3); - } else if (chain == CHAIN_2){ + } else if (chain == CHAIN_2) { config = config | (1 << 4); } else { - throw uhd::runtime_error("[ad9361_device_t] Can not read both chains synchronously"); + throw uhd::runtime_error( + "[ad9361_device_t] Can not read both chains synchronously"); } - if(direction == RX) - { + if (direction == RX) { base = 0xF0; } else { base = 0x60; } - _io_iface->poke8(base+5,config); + _io_iface->poke8(base + 5, config); std::vector<int16_t> taps; uint8_t lower_val; uint8_t higher_val; uint16_t coeff; - for(size_t i = 0;i < num_taps;i++) - { - _io_iface->poke8(base,0x00+i); - lower_val = _io_iface->peek8(base+3); - higher_val = _io_iface->peek8(base+4); - coeff = ((higher_val << 8) | lower_val); + for (size_t i = 0; i < num_taps; i++) { + _io_iface->poke8(base, 0x00 + i); + lower_val = _io_iface->peek8(base + 3); + higher_val = _io_iface->peek8(base + 4); + coeff = ((higher_val << 8) | lower_val); taps.push_back(int16_t(coeff)); } - config = (config & (~(1 << 1))); //disable filter clock - _io_iface->poke8(base+5,config); + config = (config & (~(1 << 1))); // disable filter clock + _io_iface->poke8(base + 5, config); return taps; } @@ -2594,15 +2622,15 @@ filter_info_base::sptr ad9361_device_t::_get_filter_lp_tia_sec(direction_t direc { double cutoff = 0; - if(direction == RX) - { - cutoff = 2.5 * _rx_tia_lp_bw; + if (direction == RX) { + cutoff = 2.5 * _rx_tia_lp_bw; } else { - cutoff = 5 * _tx_sec_lp_bw; + cutoff = 5 * _tx_sec_lp_bw; } - filter_info_base::sptr lp(new analog_filter_lp(filter_info_base::ANALOG_LOW_PASS, false, 0, "single-pole", cutoff, 20)); - return lp; + filter_info_base::sptr lp(new analog_filter_lp( + filter_info_base::ANALOG_LOW_PASS, false, 0, "single-pole", cutoff, 20)); + return lp; } /* @@ -2611,15 +2639,19 @@ filter_info_base::sptr ad9361_device_t::_get_filter_lp_tia_sec(direction_t direc filter_info_base::sptr ad9361_device_t::_get_filter_lp_bb(direction_t direction) { double cutoff = 0; - if(direction == RX) - { + if (direction == RX) { cutoff = 1.4 * _rx_bb_lp_bw; } else { cutoff = 1.6 * _tx_bb_lp_bw; } - filter_info_base::sptr bb_lp(new analog_filter_lp(filter_info_base::ANALOG_LOW_PASS, false, 1, "third-order Butterworth", cutoff, 60)); - return bb_lp; + filter_info_base::sptr bb_lp(new analog_filter_lp(filter_info_base::ANALOG_LOW_PASS, + false, + 1, + "third-order Butterworth", + cutoff, + 60)); + return bb_lp; } /* @@ -2642,227 +2674,272 @@ filter_info_base::sptr ad9361_device_t::_get_filter_dec_int_3(direction_t direct filter_info_base::sptr ret; - if(direction == RX) - { + if (direction == RX) { full_scale = 16384; - dec = 3; - interpol = 1; + dec = 3; + interpol = 1; enable = _io_iface->peek8(0x003); enable = ((enable >> 4) & 0x03); - taps.assign(taps_array_rx, taps_array_rx + sizeof(taps_array_rx) / sizeof(int16_t) ); + taps.assign( + taps_array_rx, taps_array_rx + sizeof(taps_array_rx) / sizeof(int16_t)); } else { full_scale = 8192; - dec = 1; - interpol = 3; + dec = 1; + interpol = 3; uint8_t use_dac_clk_div = _io_iface->peek8(0x00A); - use_dac_clk_div = ((use_dac_clk_div >> 3) & 0x01); - if(use_dac_clk_div == 1) - { + use_dac_clk_div = ((use_dac_clk_div >> 3) & 0x01); + if (use_dac_clk_div == 1) { rate = rate / 2; } enable = _io_iface->peek8(0x002); enable = ((enable >> 4) & 0x03); - if(enable == 2) //0 => int. by 1, 1 => int. by 2 (HB3), 2 => int. by 3 + if (enable == 2) // 0 => int. by 1, 1 => int. by 2 (HB3), 2 => int. by 3 { rate /= 3; } - taps.assign(taps_array_tx, taps_array_tx + sizeof(taps_array_tx) / sizeof(int16_t) ); + taps.assign( + taps_array_tx, taps_array_tx + sizeof(taps_array_tx) / sizeof(int16_t)); } - ret = filter_info_base::sptr(new digital_filter_base<int16_t>(type, (enable != 2) ? true : false, 2, rate, interpol, dec, full_scale, taps.size(), taps)); - return ret; + ret = filter_info_base::sptr(new digital_filter_base<int16_t>(type, + (enable != 2) ? true : false, + 2, + rate, + interpol, + dec, + full_scale, + taps.size(), + taps)); + return ret; } filter_info_base::sptr ad9361_device_t::_get_filter_hb_3(direction_t direction) { - uint8_t enable = 0; - double rate = _adcclock_freq; - double full_scale = 0; - size_t dec = 1; - size_t interpol = 1; + uint8_t enable = 0; + double rate = _adcclock_freq; + double full_scale = 0; + size_t dec = 1; + size_t interpol = 1; filter_info_base::filter_type type = filter_info_base::DIGITAL_I16; - int16_t taps_array_rx[] = {1, 4, 6, 4, 1}; - int16_t taps_array_tx[] = {1, 2, 1}; + int16_t taps_array_rx[] = {1, 4, 6, 4, 1}; + int16_t taps_array_tx[] = {1, 2, 1}; std::vector<int16_t> taps; - if(direction == RX) - { + if (direction == RX) { full_scale = 16; - dec = 2; + dec = 2; enable = _io_iface->peek8(0x003); enable = ((enable >> 4) & 0x03); - taps.assign(taps_array_rx, taps_array_rx + sizeof(taps_array_rx) / sizeof(int16_t) ); + taps.assign( + taps_array_rx, taps_array_rx + sizeof(taps_array_rx) / sizeof(int16_t)); } else { full_scale = 2; - interpol = 2; + interpol = 2; uint8_t use_dac_clk_div = _io_iface->peek8(0x00A); - use_dac_clk_div = ((use_dac_clk_div >> 3) & 0x01); - if(use_dac_clk_div == 1) - { + use_dac_clk_div = ((use_dac_clk_div >> 3) & 0x01); + if (use_dac_clk_div == 1) { rate = rate / 2; } enable = _io_iface->peek8(0x002); enable = ((enable >> 4) & 0x03); - if(enable == 1) - { + if (enable == 1) { rate /= 2; } - taps.assign(taps_array_tx, taps_array_tx + sizeof(taps_array_tx) / sizeof(int16_t) ); + taps.assign( + taps_array_tx, taps_array_tx + sizeof(taps_array_tx) / sizeof(int16_t)); } - filter_info_base::sptr hb = filter_info_base::sptr(new digital_filter_base<int16_t>(type, (enable != 1) ? true : false, 2, rate, interpol, dec, full_scale, taps.size(), taps)); - return hb; + filter_info_base::sptr hb = + filter_info_base::sptr(new digital_filter_base<int16_t>(type, + (enable != 1) ? true : false, + 2, + rate, + interpol, + dec, + full_scale, + taps.size(), + taps)); + return hb; } filter_info_base::sptr ad9361_device_t::_get_filter_hb_2(direction_t direction) { - uint8_t enable = 0; - double rate = _adcclock_freq; - double full_scale = 0; - size_t dec = 1; - size_t interpol = 1; + uint8_t enable = 0; + double rate = _adcclock_freq; + double full_scale = 0; + size_t dec = 1; + size_t interpol = 1; filter_info_base::filter_type type = filter_info_base::DIGITAL_I16; - int16_t taps_array[] = {-9, 0, 73, 128, 73, 0, -9}; - std::vector<int16_t> taps(taps_array, taps_array + sizeof(taps_array) / sizeof(int16_t) ); + int16_t taps_array[] = {-9, 0, 73, 128, 73, 0, -9}; + std::vector<int16_t> taps( + taps_array, taps_array + sizeof(taps_array) / sizeof(int16_t)); - digital_filter_base<int16_t>::sptr hb_3 = std::dynamic_pointer_cast<digital_filter_base<int16_t> >(_get_filter_hb_3(direction)); - digital_filter_base<int16_t>::sptr dec_int_3 = std::dynamic_pointer_cast<digital_filter_base<int16_t> >(_get_filter_dec_int_3(direction)); + digital_filter_base<int16_t>::sptr hb_3 = + std::dynamic_pointer_cast<digital_filter_base<int16_t>>( + _get_filter_hb_3(direction)); + digital_filter_base<int16_t>::sptr dec_int_3 = + std::dynamic_pointer_cast<digital_filter_base<int16_t>>( + _get_filter_dec_int_3(direction)); - if(direction == RX) - { + if (direction == RX) { full_scale = 256; - dec = 2; - enable = _io_iface->peek8(0x003); + dec = 2; + enable = _io_iface->peek8(0x003); } else { full_scale = 128; - interpol = 2; - enable = _io_iface->peek8(0x002); + interpol = 2; + enable = _io_iface->peek8(0x002); } enable = ((enable >> 3) & 0x01); - if(!(hb_3->is_bypassed())) - { - if(direction == RX) - { + if (!(hb_3->is_bypassed())) { + if (direction == RX) { rate = hb_3->get_output_rate(); - }else if (direction == TX) { + } else if (direction == TX) { rate = hb_3->get_input_rate(); - if(enable) - { + if (enable) { rate /= 2; } } - } else { //else dec3/int3 or none of them is used. - if(direction == RX) - { + } else { // else dec3/int3 or none of them is used. + if (direction == RX) { rate = dec_int_3->get_output_rate(); - }else if (direction == TX) { + } else if (direction == TX) { rate = dec_int_3->get_input_rate(); - if(enable) - { + if (enable) { rate /= 2; } } } - filter_info_base::sptr hb(new digital_filter_base<int16_t>(type, (enable == 0) ? true : false, 3, rate, interpol, dec, full_scale, taps.size(), taps)); - return hb; + filter_info_base::sptr hb(new digital_filter_base<int16_t>(type, + (enable == 0) ? true : false, + 3, + rate, + interpol, + dec, + full_scale, + taps.size(), + taps)); + return hb; } filter_info_base::sptr ad9361_device_t::_get_filter_hb_1(direction_t direction) { - uint8_t enable = 0; - double rate = 0; - double full_scale = 0; - size_t dec = 1; - size_t interpol = 1; + uint8_t enable = 0; + double rate = 0; + double full_scale = 0; + size_t dec = 1; + size_t interpol = 1; filter_info_base::filter_type type = filter_info_base::DIGITAL_I16; std::vector<int16_t> taps; - int16_t taps_rx_array[] = {-8, 0, 42, 0, -147, 0, 619, 1013, 619, 0, -147, 0, 42, 0, -8}; - int16_t taps_tx_array[] = {-53, 0, 313, 0, -1155, 0, 4989, 8192, 4989, 0, -1155, 0, 313, 0, -53}; + int16_t taps_rx_array[] = { + -8, 0, 42, 0, -147, 0, 619, 1013, 619, 0, -147, 0, 42, 0, -8}; + int16_t taps_tx_array[] = { + -53, 0, 313, 0, -1155, 0, 4989, 8192, 4989, 0, -1155, 0, 313, 0, -53}; - digital_filter_base<int16_t>::sptr hb_2 = std::dynamic_pointer_cast<digital_filter_base<int16_t> >(_get_filter_hb_2(direction)); + digital_filter_base<int16_t>::sptr hb_2 = + std::dynamic_pointer_cast<digital_filter_base<int16_t>>( + _get_filter_hb_2(direction)); - if(direction == RX) - { + if (direction == RX) { full_scale = 2048; - dec = 2; - enable = _io_iface->peek8(0x003); - enable = ((enable >> 2) & 0x01); - rate = hb_2->get_output_rate(); - taps.assign(taps_rx_array, taps_rx_array + sizeof(taps_rx_array) / sizeof(int16_t) ); + dec = 2; + enable = _io_iface->peek8(0x003); + enable = ((enable >> 2) & 0x01); + rate = hb_2->get_output_rate(); + taps.assign( + taps_rx_array, taps_rx_array + sizeof(taps_rx_array) / sizeof(int16_t)); } else if (direction == TX) { full_scale = 8192; - interpol = 2; - enable = _io_iface->peek8(0x002); - enable = ((enable >> 2) & 0x01); - rate = hb_2->get_input_rate(); - if(enable) - { + interpol = 2; + enable = _io_iface->peek8(0x002); + enable = ((enable >> 2) & 0x01); + rate = hb_2->get_input_rate(); + if (enable) { rate /= 2; } - taps.assign(taps_tx_array, taps_tx_array + sizeof(taps_tx_array) / sizeof(int16_t) ); + taps.assign( + taps_tx_array, taps_tx_array + sizeof(taps_tx_array) / sizeof(int16_t)); } - filter_info_base::sptr hb(new digital_filter_base<int16_t>(type, (enable == 0) ? true : false, 4, rate, interpol, dec, full_scale, taps.size(), taps)); - return hb; + filter_info_base::sptr hb(new digital_filter_base<int16_t>(type, + (enable == 0) ? true : false, + 4, + rate, + interpol, + dec, + full_scale, + taps.size(), + taps)); + return hb; } -filter_info_base::sptr ad9361_device_t::_get_filter_fir(direction_t direction, chain_t chain) +filter_info_base::sptr ad9361_device_t::_get_filter_fir( + direction_t direction, chain_t chain) { - double rate = 0; - size_t dec = 1; - size_t interpol = 1; + double rate = 0; + size_t dec = 1; + size_t interpol = 1; size_t max_num_taps = 128; - uint8_t enable = 1; + uint8_t enable = 1; - digital_filter_base<int16_t>::sptr hb_1 = std::dynamic_pointer_cast<digital_filter_base<int16_t> >(_get_filter_hb_1(direction)); + digital_filter_base<int16_t>::sptr hb_1 = + std::dynamic_pointer_cast<digital_filter_base<int16_t>>( + _get_filter_hb_1(direction)); - if(direction == RX) - { + if (direction == RX) { dec = _get_fir_dec_int(direction); - if(dec == 0) - { + if (dec == 0) { enable = 0; - dec = 1; + dec = 1; } interpol = 1; - rate = hb_1->get_output_rate(); - }else if (direction == TX) { + rate = hb_1->get_output_rate(); + } else if (direction == TX) { interpol = _get_fir_dec_int(direction); - if(interpol == 0) - { - enable = 0; + if (interpol == 0) { + enable = 0; interpol = 1; } - dec = 1; + dec = 1; rate = hb_1->get_input_rate(); - if(enable) - { + if (enable) { rate /= interpol; } } max_num_taps = _get_num_fir_taps(direction); - filter_info_base::sptr fir(new digital_filter_fir<int16_t>(filter_info_base::DIGITAL_FIR_I16, (enable == 0) ? true : false, 5, rate, interpol, dec, 32767, max_num_taps, _get_fir_taps(direction, chain))); + filter_info_base::sptr fir( + new digital_filter_fir<int16_t>(filter_info_base::DIGITAL_FIR_I16, + (enable == 0) ? true : false, + 5, + rate, + interpol, + dec, + 32767, + max_num_taps, + _get_fir_taps(direction, chain))); return fir; } -void ad9361_device_t::_set_filter_fir(direction_t direction, chain_t channel, filter_info_base::sptr filter) +void ad9361_device_t::_set_filter_fir( + direction_t direction, chain_t channel, filter_info_base::sptr filter) { - digital_filter_fir<int16_t>::sptr fir = std::dynamic_pointer_cast<digital_filter_fir<int16_t> >(filter); - //only write taps. Ignore everything else for now + digital_filter_fir<int16_t>::sptr fir = + std::dynamic_pointer_cast<digital_filter_fir<int16_t>>(filter); + // only write taps. Ignore everything else for now _set_fir_taps(direction, channel, fir->get_taps()); } @@ -2871,34 +2948,39 @@ void ad9361_device_t::_set_filter_fir(direction_t direction, chain_t channel, fi * _tx_analog_bw and _rx_analog_bw are not valid any more! * For useful data in those variables set_bw_filter method should be used */ -void ad9361_device_t::_set_filter_lp_bb(direction_t direction, filter_info_base::sptr filter) +void ad9361_device_t::_set_filter_lp_bb( + direction_t direction, filter_info_base::sptr filter) { analog_filter_lp::sptr lpf = std::dynamic_pointer_cast<analog_filter_lp>(filter); - double bw = lpf->get_cutoff(); - if(direction == RX) - { - //remember: this function takes rf bw as its input and calibrated to 1.4 x the given value - _rx_bb_lp_bw = _calibrate_baseband_rx_analog_filter(2 * bw / 1.4); //returns bb bw + double bw = lpf->get_cutoff(); + if (direction == RX) { + // remember: this function takes rf bw as its input and calibrated to 1.4 x the + // given value + _rx_bb_lp_bw = _calibrate_baseband_rx_analog_filter(2 * bw / 1.4); // returns bb + // bw } else { - //remember: this function takes rf bw as its input and calibrates to 1.6 x the given value + // remember: this function takes rf bw as its input and calibrates to 1.6 x the + // given value _tx_bb_lp_bw = _calibrate_baseband_tx_analog_filter(2 * bw / 1.6); } } -void ad9361_device_t::_set_filter_lp_tia_sec(direction_t direction, filter_info_base::sptr filter) +void ad9361_device_t::_set_filter_lp_tia_sec( + direction_t direction, filter_info_base::sptr filter) { analog_filter_lp::sptr lpf = std::dynamic_pointer_cast<analog_filter_lp>(filter); - double bw = lpf->get_cutoff(); - if(direction == RX) - { - //remember: this function takes rf bw as its input and calibrated to 2.5 x the given value - _rx_tia_lp_bw = _calibrate_rx_TIAs(2 * bw / 2.5); //returns bb bw + double bw = lpf->get_cutoff(); + if (direction == RX) { + // remember: this function takes rf bw as its input and calibrated to 2.5 x the + // given value + _rx_tia_lp_bw = _calibrate_rx_TIAs(2 * bw / 2.5); // returns bb bw } else { - //remember: this function takes rf bw as its input and calibrates to 5 x the given value + // remember: this function takes rf bw as its input and calibrates to 5 x the + // given value _tx_sec_lp_bw = _calibrate_secondary_tx_filter(2 * bw / 5); } } -}} +}} // namespace uhd::usrp diff --git a/host/lib/usrp/common/ad936x_manager.cpp b/host/lib/usrp/common/ad936x_manager.cpp index b57b94302..9646f0427 100644 --- a/host/lib/usrp/common/ad936x_manager.cpp +++ b/host/lib/usrp/common/ad936x_manager.cpp @@ -8,9 +8,9 @@ #include <uhd/utils/log.hpp> #include <uhdlib/usrp/common/ad936x_manager.hpp> #include <boost/functional/hash.hpp> -#include <memory> #include <chrono> #include <cmath> +#include <memory> #include <thread> using namespace uhd; diff --git a/host/lib/usrp/common/adf4001_ctrl.cpp b/host/lib/usrp/common/adf4001_ctrl.cpp index 85a13455f..a9f3c1fdb 100644 --- a/host/lib/usrp/common/adf4001_ctrl.cpp +++ b/host/lib/usrp/common/adf4001_ctrl.cpp @@ -10,71 +10,72 @@ // SPDX-License-Identifier: GPL-3.0-or-later // -#include <uhdlib/usrp/common/adf4001_ctrl.hpp> #include <uhd/utils/log.hpp> - -#include <iostream> +#include <uhdlib/usrp/common/adf4001_ctrl.hpp> #include <iomanip> +#include <iostream> using namespace uhd; using namespace uhd::usrp; -adf4001_regs_t::adf4001_regs_t(void) { - ref_counter = 0; - n = 0; - charge_pump_current_1 = 0; - charge_pump_current_2 = 0; - anti_backlash_width = ANTI_BACKLASH_WIDTH_2_9NS; - lock_detect_precision = LOCK_DETECT_PRECISION_3CYC; - charge_pump_gain = CHARGE_PUMP_GAIN_1; - counter_reset = COUNTER_RESET_NORMAL; - power_down = POWER_DOWN_NORMAL; - muxout = MUXOUT_TRISTATE_OUT; +adf4001_regs_t::adf4001_regs_t(void) +{ + ref_counter = 0; + n = 0; + charge_pump_current_1 = 0; + charge_pump_current_2 = 0; + anti_backlash_width = ANTI_BACKLASH_WIDTH_2_9NS; + lock_detect_precision = LOCK_DETECT_PRECISION_3CYC; + charge_pump_gain = CHARGE_PUMP_GAIN_1; + counter_reset = COUNTER_RESET_NORMAL; + power_down = POWER_DOWN_NORMAL; + muxout = MUXOUT_TRISTATE_OUT; phase_detector_polarity = PHASE_DETECTOR_POLARITY_NEGATIVE; - charge_pump_mode = CHARGE_PUMP_TRISTATE; - fastlock_mode = FASTLOCK_MODE_DISABLED; - timer_counter_control = TIMEOUT_3CYC; + charge_pump_mode = CHARGE_PUMP_TRISTATE; + fastlock_mode = FASTLOCK_MODE_DISABLED; + timer_counter_control = TIMEOUT_3CYC; } -uint32_t adf4001_regs_t::get_reg(uint8_t addr) { +uint32_t adf4001_regs_t::get_reg(uint8_t addr) +{ uint32_t reg = 0; switch (addr) { - case 0: - reg |= (uint32_t(ref_counter) & 0x003FFF) << 2; - reg |= (uint32_t(anti_backlash_width) & 0x000003) << 16; - reg |= (uint32_t(lock_detect_precision) & 0x000001) << 20; - break; - case 1: - reg |= (uint32_t(n) & 0x001FFF) << 8; - reg |= (uint32_t(charge_pump_gain) & 0x000001) << 21; - break; - case 2: - reg |= (uint32_t(counter_reset) & 0x000001) << 2; - reg |= (uint32_t(power_down) & 0x000001) << 3; - reg |= (uint32_t(muxout) & 0x000007) << 4; - reg |= (uint32_t(phase_detector_polarity) & 0x000001) << 7; - reg |= (uint32_t(charge_pump_mode) & 0x000001) << 8; - reg |= (uint32_t(fastlock_mode) & 0x000003) << 9; - reg |= (uint32_t(timer_counter_control) & 0x00000F) << 11; - reg |= (uint32_t(charge_pump_current_1) & 0x000007) << 15; - reg |= (uint32_t(charge_pump_current_2) & 0x000007) << 18; - reg |= (uint32_t(power_down) & 0x000002) << 20; - break; - case 3: - reg |= (uint32_t(counter_reset) & 0x000001) << 2; - reg |= (uint32_t(power_down) & 0x000001) << 3; - reg |= (uint32_t(muxout) & 0x000007) << 4; - reg |= (uint32_t(phase_detector_polarity) & 0x000001) << 7; - reg |= (uint32_t(charge_pump_mode) & 0x000001) << 8; - reg |= (uint32_t(fastlock_mode) & 0x000003) << 9; - reg |= (uint32_t(timer_counter_control) & 0x00000F) << 11; - reg |= (uint32_t(charge_pump_current_1) & 0x000007) << 15; - reg |= (uint32_t(charge_pump_current_2) & 0x000007) << 18; - reg |= (uint32_t(power_down) & 0x000002) << 20; - break; - default: - break; + case 0: + reg |= (uint32_t(ref_counter) & 0x003FFF) << 2; + reg |= (uint32_t(anti_backlash_width) & 0x000003) << 16; + reg |= (uint32_t(lock_detect_precision) & 0x000001) << 20; + break; + case 1: + reg |= (uint32_t(n) & 0x001FFF) << 8; + reg |= (uint32_t(charge_pump_gain) & 0x000001) << 21; + break; + case 2: + reg |= (uint32_t(counter_reset) & 0x000001) << 2; + reg |= (uint32_t(power_down) & 0x000001) << 3; + reg |= (uint32_t(muxout) & 0x000007) << 4; + reg |= (uint32_t(phase_detector_polarity) & 0x000001) << 7; + reg |= (uint32_t(charge_pump_mode) & 0x000001) << 8; + reg |= (uint32_t(fastlock_mode) & 0x000003) << 9; + reg |= (uint32_t(timer_counter_control) & 0x00000F) << 11; + reg |= (uint32_t(charge_pump_current_1) & 0x000007) << 15; + reg |= (uint32_t(charge_pump_current_2) & 0x000007) << 18; + reg |= (uint32_t(power_down) & 0x000002) << 20; + break; + case 3: + reg |= (uint32_t(counter_reset) & 0x000001) << 2; + reg |= (uint32_t(power_down) & 0x000001) << 3; + reg |= (uint32_t(muxout) & 0x000007) << 4; + reg |= (uint32_t(phase_detector_polarity) & 0x000001) << 7; + reg |= (uint32_t(charge_pump_mode) & 0x000001) << 8; + reg |= (uint32_t(fastlock_mode) & 0x000003) << 9; + reg |= (uint32_t(timer_counter_control) & 0x00000F) << 11; + reg |= (uint32_t(charge_pump_current_1) & 0x000007) << 15; + reg |= (uint32_t(charge_pump_current_2) & 0x000007) << 18; + reg |= (uint32_t(power_down) & 0x000002) << 20; + break; + default: + break; } reg |= (uint32_t(addr) & 0x03); @@ -83,30 +84,30 @@ uint32_t adf4001_regs_t::get_reg(uint8_t addr) { } -adf4001_ctrl::adf4001_ctrl(uhd::spi_iface::sptr _spi, int slaveno): - spi_iface(_spi), - slaveno(slaveno) - { - +adf4001_ctrl::adf4001_ctrl(uhd::spi_iface::sptr _spi, int slaveno) + : spi_iface(_spi), slaveno(slaveno) +{ spi_config.mosi_edge = spi_config_t::EDGE_RISE; - //set defaults - adf4001_regs.ref_counter = 1; - adf4001_regs.n = 4; + // set defaults + adf4001_regs.ref_counter = 1; + adf4001_regs.n = 4; adf4001_regs.charge_pump_current_1 = 7; adf4001_regs.charge_pump_current_2 = 7; - adf4001_regs.muxout = adf4001_regs_t::MUXOUT_DLD; - adf4001_regs.counter_reset = adf4001_regs_t::COUNTER_RESET_NORMAL; - adf4001_regs.phase_detector_polarity = adf4001_regs_t::PHASE_DETECTOR_POLARITY_POSITIVE; + adf4001_regs.muxout = adf4001_regs_t::MUXOUT_DLD; + adf4001_regs.counter_reset = adf4001_regs_t::COUNTER_RESET_NORMAL; + adf4001_regs.phase_detector_polarity = + adf4001_regs_t::PHASE_DETECTOR_POLARITY_POSITIVE; adf4001_regs.charge_pump_mode = adf4001_regs_t::CHARGE_PUMP_TRISTATE; - //everything else should be defaults + // everything else should be defaults program_regs(); } -void adf4001_ctrl::set_lock_to_ext_ref(bool external) { - if(external) { +void adf4001_ctrl::set_lock_to_ext_ref(bool external) +{ + if (external) { adf4001_regs.charge_pump_mode = adf4001_regs_t::CHARGE_PUMP_NORMAL; } else { adf4001_regs.charge_pump_mode = adf4001_regs_t::CHARGE_PUMP_TRISTATE; @@ -115,27 +116,25 @@ void adf4001_ctrl::set_lock_to_ext_ref(bool external) { program_regs(); } -void adf4001_ctrl::program_regs(void) { - //no control over CE, only LE, therefore we use the initialization latch method +void adf4001_ctrl::program_regs(void) +{ + // no control over CE, only LE, therefore we use the initialization latch method write_reg(3); - //conduct a function latch (2) + // conduct a function latch (2) write_reg(2); - //write R counter latch (0) + // write R counter latch (0) write_reg(0); - //write N counter latch (1) + // write N counter latch (1) write_reg(1); } -void adf4001_ctrl::write_reg(uint8_t addr) { - uint32_t reg = adf4001_regs.get_reg(addr); //load the reg data +void adf4001_ctrl::write_reg(uint8_t addr) +{ + uint32_t reg = adf4001_regs.get_reg(addr); // load the reg data - spi_iface->transact_spi(slaveno, - spi_config, - reg, - 24, - false); + spi_iface->transact_spi(slaveno, spi_config, reg, 24, false); } diff --git a/host/lib/usrp/common/adf435x.cpp b/host/lib/usrp/common/adf435x.cpp index 6d59befaa..4b5f9ac7e 100644 --- a/host/lib/usrp/common/adf435x.cpp +++ b/host/lib/usrp/common/adf435x.cpp @@ -9,9 +9,7 @@ using namespace uhd; -adf435x_iface::~adf435x_iface() -{ -} +adf435x_iface::~adf435x_iface() {} adf435x_iface::sptr adf435x_iface::make_adf4350(write_fn_t write) { diff --git a/host/lib/usrp/common/apply_corrections.cpp b/host/lib/usrp/common/apply_corrections.cpp index b57ace71b..b75ab7d95 100644 --- a/host/lib/usrp/common/apply_corrections.cpp +++ b/host/lib/usrp/common/apply_corrections.cpp @@ -5,16 +5,16 @@ // SPDX-License-Identifier: GPL-3.0-or-later // -#include <uhdlib/usrp/common/apply_corrections.hpp> +#include <uhd/types/dict.hpp> #include <uhd/usrp/dboard_eeprom.hpp> -#include <uhd/utils/paths.hpp> -#include <uhd/utils/log.hpp> #include <uhd/utils/csv.hpp> -#include <uhd/types/dict.hpp> +#include <uhd/utils/log.hpp> +#include <uhd/utils/paths.hpp> +#include <uhdlib/usrp/common/apply_corrections.hpp> #include <boost/filesystem.hpp> #include <boost/thread/mutex.hpp> -#include <cstdio> #include <complex> +#include <cstdio> #include <fstream> namespace fs = boost::filesystem; @@ -24,24 +24,27 @@ boost::mutex corrections_mutex; /*********************************************************************** * Helper routines **********************************************************************/ -static double linear_interp(double x, double x0, double y0, double x1, double y1){ - return y0 + (x - x0)*(y1 - y0)/(x1 - x0); +static double linear_interp(double x, double x0, double y0, double x1, double y1) +{ + return y0 + (x - x0) * (y1 - y0) / (x1 - x0); } /*********************************************************************** * FE apply corrections implementation **********************************************************************/ -struct fe_cal_t{ +struct fe_cal_t +{ double lo_freq; double iq_corr_real; double iq_corr_imag; }; -static bool fe_cal_comp(fe_cal_t a, fe_cal_t b){ +static bool fe_cal_comp(fe_cal_t a, fe_cal_t b) +{ return (a.lo_freq < b.lo_freq); } -static uhd::dict<std::string, std::vector<fe_cal_t> > fe_cal_cache; +static uhd::dict<std::string, std::vector<fe_cal_t>> fe_cal_cache; static bool is_same_freq(const double f1, const double f2) { @@ -50,36 +53,46 @@ static bool is_same_freq(const double f1, const double f2) } static std::complex<double> get_fe_correction( - const std::string &key, const double lo_freq -){ - const std::vector<fe_cal_t> &datas = fe_cal_cache[key]; - if (datas.empty()) throw uhd::runtime_error("empty calibration table " + key); + const std::string& key, const double lo_freq) +{ + const std::vector<fe_cal_t>& datas = fe_cal_cache[key]; + if (datas.empty()) + throw uhd::runtime_error("empty calibration table " + key); - //search for lo freq + // search for lo freq size_t lo_index = 0; - size_t hi_index = datas.size()-1; - for (size_t i = 0; i < datas.size(); i++){ - if (is_same_freq(datas[i].lo_freq, lo_freq)) - { + size_t hi_index = datas.size() - 1; + for (size_t i = 0; i < datas.size(); i++) { + if (is_same_freq(datas[i].lo_freq, lo_freq)) { hi_index = i; lo_index = i; break; } - if (datas[i].lo_freq > lo_freq){ + if (datas[i].lo_freq > lo_freq) { hi_index = i; break; } lo_index = i; } - if (lo_index == 0) return std::complex<double>(datas[lo_index].iq_corr_real, datas[lo_index].iq_corr_imag); - if (hi_index == lo_index) return std::complex<double>(datas[hi_index].iq_corr_real, datas[hi_index].iq_corr_imag); - - //interpolation time - return std::complex<double>( - linear_interp(lo_freq, datas[lo_index].lo_freq, datas[lo_index].iq_corr_real, datas[hi_index].lo_freq, datas[hi_index].iq_corr_real), - linear_interp(lo_freq, datas[lo_index].lo_freq, datas[lo_index].iq_corr_imag, datas[hi_index].lo_freq, datas[hi_index].iq_corr_imag) - ); + if (lo_index == 0) + return std::complex<double>( + datas[lo_index].iq_corr_real, datas[lo_index].iq_corr_imag); + if (hi_index == lo_index) + return std::complex<double>( + datas[hi_index].iq_corr_real, datas[hi_index].iq_corr_imag); + + // interpolation time + return std::complex<double>(linear_interp(lo_freq, + datas[lo_index].lo_freq, + datas[lo_index].iq_corr_real, + datas[hi_index].lo_freq, + datas[hi_index].iq_corr_real), + linear_interp(lo_freq, + datas[lo_index].lo_freq, + datas[lo_index].iq_corr_imag, + datas[hi_index].lo_freq, + datas[hi_index].iq_corr_imag)); } static void apply_fe_corrections(uhd::property_tree::sptr sub_tree, @@ -88,43 +101,45 @@ static void apply_fe_corrections(uhd::property_tree::sptr sub_tree, const std::string& file_prefix, const double lo_freq) { - //make the calibration file path + // make the calibration file path const fs::path cal_data_path = fs::path(uhd::get_app_path()) / ".uhd" / "cal" / (file_prefix + db_serial + ".csv"); - if (not fs::exists(cal_data_path)) return; + if (not fs::exists(cal_data_path)) + return; - //parse csv file or get from cache - if (not fe_cal_cache.has_key(cal_data_path.string())){ + // parse csv file or get from cache + if (not fe_cal_cache.has_key(cal_data_path.string())) { std::ifstream cal_data(cal_data_path.string().c_str()); const uhd::csv::rows_type rows = uhd::csv::to_rows(cal_data); - bool read_data = false, skip_next = false;; + bool read_data = false, skip_next = false; + ; std::vector<fe_cal_t> datas; - for(const uhd::csv::row_type &row: rows){ - if (not read_data and not row.empty() and row[0] == "DATA STARTS HERE"){ + for (const uhd::csv::row_type& row : rows) { + if (not read_data and not row.empty() and row[0] == "DATA STARTS HERE") { read_data = true; skip_next = true; continue; } - if (not read_data) continue; - if (skip_next){ + if (not read_data) + continue; + if (skip_next) { skip_next = false; continue; } fe_cal_t data; - std::sscanf(row[0].c_str(), "%lf" , &data.lo_freq); - std::sscanf(row[1].c_str(), "%lf" , &data.iq_corr_real); - std::sscanf(row[2].c_str(), "%lf" , &data.iq_corr_imag); + std::sscanf(row[0].c_str(), "%lf", &data.lo_freq); + std::sscanf(row[1].c_str(), "%lf", &data.iq_corr_real); + std::sscanf(row[2].c_str(), "%lf", &data.iq_corr_imag); datas.push_back(data); } std::sort(datas.begin(), datas.end(), fe_cal_comp); fe_cal_cache[cal_data_path.string()] = datas; UHD_LOGGER_INFO("CAL") << "Calibration data loaded: " << cal_data_path.string(); - } - sub_tree->access<std::complex<double> >(fe_path) - .set(get_fe_correction(cal_data_path.string(), lo_freq)); + sub_tree->access<std::complex<double>>(fe_path).set( + get_fe_correction(cal_data_path.string(), lo_freq)); } /*********************************************************************** @@ -139,7 +154,7 @@ void uhd::usrp::apply_tx_fe_corrections( // overloading to work according to rfn ) { boost::mutex::scoped_lock l(corrections_mutex); - try{ + try { apply_fe_corrections(sub_tree, db_serial, tx_fe_corr_path + "/iq_balance/value", @@ -150,17 +165,17 @@ void uhd::usrp::apply_tx_fe_corrections( // overloading to work according to rfn tx_fe_corr_path + "/dc_offset/value", "tx_dc_cal_v0.2_", lo_freq); - } - catch(const std::exception &e){ + } catch (const std::exception& e) { UHD_LOGGER_ERROR("CAL") << "Failure in apply_tx_fe_corrections: " << e.what(); } } void uhd::usrp::apply_tx_fe_corrections( - property_tree::sptr sub_tree, //starts at mboards/x - const std::string &slot, //name of dboard slot - const double lo_freq //actual lo freq -){ + property_tree::sptr sub_tree, // starts at mboards/x + const std::string& slot, // name of dboard slot + const double lo_freq // actual lo freq +) +{ boost::mutex::scoped_lock l(corrections_mutex); // extract eeprom serial @@ -168,7 +183,7 @@ void uhd::usrp::apply_tx_fe_corrections( const std::string db_serial = sub_tree->access<uhd::usrp::dboard_eeprom_t>(db_path).get().serial; - try{ + try { apply_fe_corrections(sub_tree, db_serial, "tx_frontends/" + slot + "/iq_balance/value", @@ -179,8 +194,7 @@ void uhd::usrp::apply_tx_fe_corrections( "tx_frontends/" + slot + "/dc_offset/value", "tx_dc_cal_v0.2_", lo_freq); - } - catch(const std::exception &e){ + } catch (const std::exception& e) { UHD_LOGGER_ERROR("CAL") << "Failure in apply_tx_fe_corrections: " << e.what(); } } @@ -194,35 +208,34 @@ void uhd::usrp::apply_rx_fe_corrections( // overloading to work according to rfn ) { boost::mutex::scoped_lock l(corrections_mutex); - try{ + try { apply_fe_corrections(sub_tree, db_serial, rx_fe_corr_path + "/iq_balance/value", "rx_iq_cal_v0.2_", lo_freq); - } - catch(const std::exception &e){ + } catch (const std::exception& e) { UHD_LOGGER_ERROR("CAL") << "Failure in apply_tx_fe_corrections: " << e.what(); } } void uhd::usrp::apply_rx_fe_corrections( - property_tree::sptr sub_tree, //starts at mboards/x - const std::string &slot, //name of dboard slot - const double lo_freq //actual lo freq -){ + property_tree::sptr sub_tree, // starts at mboards/x + const std::string& slot, // name of dboard slot + const double lo_freq // actual lo freq +) +{ boost::mutex::scoped_lock l(corrections_mutex); const uhd::fs_path db_path = "dboards/" + slot + "/rx_eeprom"; const std::string db_serial = sub_tree->access<uhd::usrp::dboard_eeprom_t>(db_path).get().serial; - try{ + try { apply_fe_corrections(sub_tree, db_serial, "rx_frontends/" + slot + "/iq_balance/value", "rx_iq_cal_v0.2_", lo_freq); - } - catch(const std::exception &e){ + } catch (const std::exception& e) { UHD_LOGGER_ERROR("CAL") << "Failure in apply_rx_fe_corrections: " << e.what(); } } diff --git a/host/lib/usrp/common/fx2_ctrl.cpp b/host/lib/usrp/common/fx2_ctrl.cpp index 77501d981..cbb108dae 100644 --- a/host/lib/usrp/common/fx2_ctrl.cpp +++ b/host/lib/usrp/common/fx2_ctrl.cpp @@ -5,19 +5,19 @@ // SPDX-License-Identifier: GPL-3.0-or-later // -#include <uhdlib/usrp/common/fx2_ctrl.hpp> -#include <uhd/utils/log.hpp> #include <uhd/exception.hpp> #include <uhd/transport/usb_control.hpp> -#include <boost/functional/hash.hpp> +#include <uhd/utils/log.hpp> +#include <uhdlib/usrp/common/fx2_ctrl.hpp> #include <stdint.h> +#include <boost/functional/hash.hpp> +#include <chrono> +#include <cstring> #include <fstream> #include <sstream> #include <string> -#include <vector> -#include <cstring> -#include <chrono> #include <thread> +#include <vector> using namespace uhd; using namespace uhd::usrp; @@ -37,10 +37,10 @@ typedef uint32_t hash_type; * \param filename file used to generate hash value * \return hash value in a size_t type */ -static hash_type generate_hash(const char *filename) +static hash_type generate_hash(const char* filename) { std::ifstream file(filename); - if (not file){ + if (not file) { throw uhd::io_error(std::string("cannot open input file ") + filename); } @@ -51,7 +51,7 @@ static hash_type generate_hash(const char *filename) boost::hash_combine(hash, ch); } - if (not file.eof()){ + if (not file.eof()) { throw uhd::io_error(std::string("file error ") + filename); } @@ -65,9 +65,8 @@ static hash_type generate_hash(const char *filename) * \param record a line from an Intel HEX file * \return true if record is valid, false otherwise */ -static bool checksum(std::string *record) +static bool checksum(std::string* record) { - size_t len = record->length(); unsigned int i; unsigned char sum = 0; @@ -79,9 +78,9 @@ static bool checksum(std::string *record) } if (sum == 0) - return true; + return true; else - return false; + return false; } @@ -95,9 +94,11 @@ static bool checksum(std::string *record) * \param data output data * \return true if record is sucessfully read, false on error */ -bool parse_record(std::string *record, unsigned int &len, - unsigned int &addr, unsigned int &type, - unsigned char* data) +bool parse_record(std::string* record, + unsigned int& len, + unsigned int& addr, + unsigned int& type, + unsigned char* data) { unsigned int i; std::string _data; @@ -110,12 +111,12 @@ bool parse_record(std::string *record, unsigned int &len, std::istringstream(record->substr(3, 4)) >> std::hex >> addr; std::istringstream(record->substr(7, 2)) >> std::hex >> type; - if (len > (2 * (record->length() - 9))) // sanity check to prevent buffer overrun + if (len > (2 * (record->length() - 9))) // sanity check to prevent buffer overrun return false; for (i = 0; i < len; i++) { std::istringstream(record->substr(9 + 2 * i, 2)) >> std::hex >> val; - data[i] = (unsigned char) val; + data[i] = (unsigned char)val; } return true; @@ -125,33 +126,37 @@ bool parse_record(std::string *record, unsigned int &len, /*! * USRP control implementation for device discovery and configuration */ -class fx2_ctrl_impl : public fx2_ctrl { +class fx2_ctrl_impl : public fx2_ctrl +{ public: fx2_ctrl_impl(uhd::transport::usb_control::sptr ctrl_transport) { _ctrl_transport = ctrl_transport; } - void usrp_fx2_reset(void){ + void usrp_fx2_reset(void) + { unsigned char reset_y = 1; unsigned char reset_n = 0; usrp_control_write(FX2_FIRMWARE_LOAD, 0xe600, 0, &reset_y, 1); usrp_control_write(FX2_FIRMWARE_LOAD, 0xe600, 0, &reset_n, 1); - //wait for things to settle + // wait for things to settle std::this_thread::sleep_for(std::chrono::milliseconds(2000)); } void usrp_load_firmware(std::string filestring, bool force) { - const char *filename = filestring.c_str(); + const char* filename = filestring.c_str(); hash_type hash = generate_hash(filename); - hash_type loaded_hash; usrp_get_firmware_hash(loaded_hash); + hash_type loaded_hash; + usrp_get_firmware_hash(loaded_hash); - if (not force and (hash == loaded_hash)) return; + if (not force and (hash == loaded_hash)) + return; - //FIXME: verify types + // FIXME: verify types unsigned int len; unsigned int addr; unsigned int type; @@ -167,54 +172,59 @@ public: unsigned char reset_y = 1; unsigned char reset_n = 0; - //hit the reset line - if (load_img_msg) UHD_LOGGER_INFO("FX2") << "Loading firmware image: " << filestring << "..."; + // hit the reset line + if (load_img_msg) + UHD_LOGGER_INFO("FX2") << "Loading firmware image: " << filestring << "..."; usrp_control_write(FX2_FIRMWARE_LOAD, 0xe600, 0, &reset_y, 1); while (!file.eof()) { - std::string record; - file >> record; + std::string record; + file >> record; if (!(record.length() > 0)) continue; - //check for valid record - if (not checksum(&record) or not parse_record(&record, len, addr, type, data)) { + // check for valid record + if (not checksum(&record) + or not parse_record(&record, len, addr, type, data)) { throw uhd::io_error("usrp_load_firmware: bad record checksum"); } - //type 0x00 is data + // type 0x00 is data if (type == 0x00) { int ret = usrp_control_write(FX2_FIRMWARE_LOAD, addr, 0, data, len); - if (ret < 0) throw uhd::io_error("usrp_load_firmware: usrp_control_write failed"); + if (ret < 0) + throw uhd::io_error("usrp_load_firmware: usrp_control_write failed"); } - //type 0x01 is end + // type 0x01 is end else if (type == 0x01) { - usrp_set_firmware_hash(hash); //set hash before reset + usrp_set_firmware_hash(hash); // set hash before reset usrp_control_write(FX2_FIRMWARE_LOAD, 0xe600, 0, &reset_n, 1); file.close(); - //wait for things to settle + // wait for things to settle std::this_thread::sleep_for(std::chrono::milliseconds(1000)); - if (load_img_msg) UHD_LOGGER_INFO("FX2") << "Firmware loaded"; + if (load_img_msg) + UHD_LOGGER_INFO("FX2") << "Firmware loaded"; return; } - //type anything else is unhandled + // type anything else is unhandled else { throw uhd::io_error("usrp_load_firmware: unsupported record"); } } - //file did not end + // file did not end throw uhd::io_error("usrp_load_firmware: bad record"); } - void usrp_init(void){ - //disable + void usrp_init(void) + { + // disable usrp_rx_enable(false); usrp_tx_enable(false); - //toggle resets + // toggle resets usrp_rx_reset(true); usrp_tx_reset(true); usrp_rx_reset(false); @@ -223,33 +233,37 @@ public: void usrp_load_fpga(std::string filestring) { - const char *filename = filestring.c_str(); + const char* filename = filestring.c_str(); hash_type hash = generate_hash(filename); - hash_type loaded_hash; usrp_get_fpga_hash(loaded_hash); + hash_type loaded_hash; + usrp_get_fpga_hash(loaded_hash); - if (hash == loaded_hash) return; + if (hash == loaded_hash) + return; const int ep0_size = 64; unsigned char buf[ep0_size]; - if (load_img_msg) UHD_LOGGER_INFO("FX2") << "Loading FPGA image: " << filestring << "..."; + if (load_img_msg) + UHD_LOGGER_INFO("FX2") << "Loading FPGA image: " << filestring << "..."; std::ifstream file; file.open(filename, std::ios::in | std::ios::binary); if (not file.good()) { throw uhd::io_error("usrp_load_fpga: cannot open fpga input file"); } - usrp_fpga_reset(true); //holding the fpga in reset while loading + usrp_fpga_reset(true); // holding the fpga in reset while loading if (usrp_control_write_cmd(VRQ_FPGA_LOAD, 0, FL_BEGIN) < 0) { throw uhd::io_error("usrp_load_fpga: fpga load error"); } while (not file.eof()) { - file.read((char *)buf, sizeof(buf)); + file.read((char*)buf, sizeof(buf)); const std::streamsize n = file.gcount(); - if(n == 0) continue; + if (n == 0) + continue; int ret = usrp_control_write(VRQ_FPGA_LOAD, 0, FL_XFER, buf, uint16_t(n)); if (ret < 0 or std::streamsize(ret) != n) { throw uhd::io_error("usrp_load_fpga: fpga load error"); @@ -262,16 +276,18 @@ public: usrp_set_fpga_hash(hash); - usrp_fpga_reset(false); //done loading, take fpga out of reset + usrp_fpga_reset(false); // done loading, take fpga out of reset file.close(); - if (load_img_msg) UHD_LOGGER_INFO("FX2") << "FPGA image loaded"; + if (load_img_msg) + UHD_LOGGER_INFO("FX2") << "FPGA image loaded"; } void usrp_load_eeprom(std::string filestring) { - if (load_img_msg) UHD_LOGGER_INFO("FX2") << "Loading EEPROM image: " << filestring << "..."; - const char *filename = filestring.c_str(); + if (load_img_msg) + UHD_LOGGER_INFO("FX2") << "Loading EEPROM image: " << filestring << "..."; + const char* filename = filestring.c_str(); const uint16_t i2c_addr = 0x50; unsigned int addr; @@ -285,19 +301,20 @@ public: throw uhd::io_error("usrp_load_eeprom: cannot open EEPROM input file"); } - file.read((char *)data, 256); + file.read((char*)data, 256); std::streamsize len = file.gcount(); - if(len == 256) { + if (len == 256) { throw uhd::io_error("usrp_load_eeprom: image size too large"); } const int pagesize = 16; - addr = 0; - while(len > 0) { + addr = 0; + while (len > 0) { sendbuf[0] = addr; - memcpy(sendbuf+1, &data[addr], len > pagesize ? pagesize : size_t(len)); - int ret = usrp_i2c_write(i2c_addr, sendbuf, (len > pagesize ? pagesize : size_t(len))+1); + memcpy(sendbuf + 1, &data[addr], len > pagesize ? pagesize : size_t(len)); + int ret = usrp_i2c_write( + i2c_addr, sendbuf, (len > pagesize ? pagesize : size_t(len)) + 1); if (ret < 0) { throw uhd::io_error("usrp_load_eeprom: usrp_i2c_write failed"); } @@ -306,7 +323,8 @@ public: std::this_thread::sleep_for(std::chrono::milliseconds(100)); } file.close(); - if (load_img_msg) UHD_LOGGER_INFO("FX2") << "EEPROM image loaded"; + if (load_img_msg) + UHD_LOGGER_INFO("FX2") << "EEPROM image loaded"; } @@ -316,32 +334,39 @@ public: } - void usrp_get_firmware_hash(hash_type &hash) + void usrp_get_firmware_hash(hash_type& hash) { - UHD_ASSERT_THROW(usrp_control_read(0xa0, USRP_HASH_SLOT_0_ADDR, 0, - (unsigned char*) &hash, sizeof(hash)) >= 0); + UHD_ASSERT_THROW( + usrp_control_read( + 0xa0, USRP_HASH_SLOT_0_ADDR, 0, (unsigned char*)&hash, sizeof(hash)) + >= 0); } void usrp_set_firmware_hash(hash_type hash) { - UHD_ASSERT_THROW(usrp_control_write(0xa0, USRP_HASH_SLOT_0_ADDR, 0, - (unsigned char*) &hash, sizeof(hash)) >= 0); - + UHD_ASSERT_THROW( + usrp_control_write( + 0xa0, USRP_HASH_SLOT_0_ADDR, 0, (unsigned char*)&hash, sizeof(hash)) + >= 0); } - void usrp_get_fpga_hash(hash_type &hash) + void usrp_get_fpga_hash(hash_type& hash) { - UHD_ASSERT_THROW(usrp_control_read(0xa0, USRP_HASH_SLOT_1_ADDR, 0, - (unsigned char*) &hash, sizeof(hash)) >= 0); + UHD_ASSERT_THROW( + usrp_control_read( + 0xa0, USRP_HASH_SLOT_1_ADDR, 0, (unsigned char*)&hash, sizeof(hash)) + >= 0); } void usrp_set_fpga_hash(hash_type hash) { - UHD_ASSERT_THROW(usrp_control_write(0xa0, USRP_HASH_SLOT_1_ADDR, 0, - (unsigned char*) &hash, sizeof(hash)) >= 0); + UHD_ASSERT_THROW( + usrp_control_write( + 0xa0, USRP_HASH_SLOT_1_ADDR, 0, (unsigned char*)&hash, sizeof(hash)) + >= 0); } void usrp_tx_enable(bool on) @@ -373,32 +398,32 @@ public: } int usrp_control_write(uint8_t request, - uint16_t value, - uint16_t index, - unsigned char *buff, - uint16_t length) + uint16_t value, + uint16_t index, + unsigned char* buff, + uint16_t length) { - return _ctrl_transport->submit(VRT_VENDOR_OUT, // bmReqeustType - request, // bRequest - value, // wValue - index, // wIndex - buff, // data - length); // wLength + return _ctrl_transport->submit(VRT_VENDOR_OUT, // bmReqeustType + request, // bRequest + value, // wValue + index, // wIndex + buff, // data + length); // wLength } int usrp_control_read(uint8_t request, - uint16_t value, - uint16_t index, - unsigned char *buff, - uint16_t length) + uint16_t value, + uint16_t index, + unsigned char* buff, + uint16_t length) { - return _ctrl_transport->submit(VRT_VENDOR_IN, // bmReqeustType - request, // bRequest - value, // wValue - index, // wIndex - buff, // data - length); // wLength + return _ctrl_transport->submit(VRT_VENDOR_IN, // bmReqeustType + request, // bRequest + value, // wValue + index, // wIndex + buff, // data + length); // wLength } @@ -407,33 +432,31 @@ public: return usrp_control_write(request, value, index, 0, 0); } - byte_vector_t read_eeprom( - uint16_t addr, - uint16_t offset, - size_t num_bytes - ){ + byte_vector_t read_eeprom(uint16_t addr, uint16_t offset, size_t num_bytes) + { this->write_i2c(addr, byte_vector_t(1, uint8_t(offset))); return this->read_i2c(addr, num_bytes); } - int usrp_i2c_write(uint16_t i2c_addr, unsigned char *buf, uint16_t len) + int usrp_i2c_write(uint16_t i2c_addr, unsigned char* buf, uint16_t len) { return usrp_control_write(VRQ_I2C_WRITE, i2c_addr, 0, buf, len); } - int usrp_i2c_read(uint16_t i2c_addr, unsigned char *buf, uint16_t len) + int usrp_i2c_read(uint16_t i2c_addr, unsigned char* buf, uint16_t len) { return usrp_control_read(VRQ_I2C_READ, i2c_addr, 0, buf, len); } - static const bool iface_debug = false; + static const bool iface_debug = false; static const size_t max_i2c_data_bytes = 64; - void write_i2c(uint16_t addr, const byte_vector_t &bytes) + void write_i2c(uint16_t addr, const byte_vector_t& bytes) { UHD_ASSERT_THROW(bytes.size() < max_i2c_data_bytes); - int ret = this->usrp_i2c_write(addr, (unsigned char *)&bytes.front(), bytes.size()); + int ret = + this->usrp_i2c_write(addr, (unsigned char*)&bytes.front(), bytes.size()); if (iface_debug && (ret < 0)) uhd::runtime_error("USRP: failed i2c write"); @@ -441,15 +464,15 @@ public: byte_vector_t read_i2c(uint16_t addr, size_t num_bytes) { - UHD_ASSERT_THROW(num_bytes < max_i2c_data_bytes); + UHD_ASSERT_THROW(num_bytes < max_i2c_data_bytes); - byte_vector_t bytes(num_bytes); - int ret = this->usrp_i2c_read(addr, (unsigned char *)&bytes.front(), num_bytes); + byte_vector_t bytes(num_bytes); + int ret = this->usrp_i2c_read(addr, (unsigned char*)&bytes.front(), num_bytes); - if (iface_debug && ((ret < 0) || (unsigned)ret < (num_bytes))) - uhd::runtime_error("USRP: failed i2c read"); + if (iface_debug && ((ret < 0) || (unsigned)ret < (num_bytes))) + uhd::runtime_error("USRP: failed i2c read"); - return bytes; + return bytes; } @@ -460,7 +483,7 @@ private: /*********************************************************************** * Public make function for fx2_ctrl interface **********************************************************************/ -fx2_ctrl::sptr fx2_ctrl::make(uhd::transport::usb_control::sptr ctrl_transport){ +fx2_ctrl::sptr fx2_ctrl::make(uhd::transport::usb_control::sptr ctrl_transport) +{ return sptr(new fx2_ctrl_impl(ctrl_transport)); } - diff --git a/host/lib/usrp/common/io_service_args.cpp b/host/lib/usrp/common/io_service_args.cpp index 8a55b8ee0..8be1ff89b 100644 --- a/host/lib/usrp/common/io_service_args.cpp +++ b/host/lib/usrp/common/io_service_args.cpp @@ -58,16 +58,18 @@ io_service_args_t read_io_service_args( io_service_args_t io_srv_args; std::string tmp_str, default_str; - io_srv_args.recv_offload = get_bool_arg(args, recv_offload_str, defaults.recv_offload); - io_srv_args.send_offload = get_bool_arg(args, send_offload_str, defaults.send_offload); + io_srv_args.recv_offload = + get_bool_arg(args, recv_offload_str, defaults.recv_offload); + io_srv_args.send_offload = + get_bool_arg(args, send_offload_str, defaults.send_offload); io_srv_args.recv_offload_wait_mode = get_wait_mode_arg( args, recv_offload_wait_mode_str, defaults.recv_offload_wait_mode); io_srv_args.send_offload_wait_mode = get_wait_mode_arg( args, send_offload_wait_mode_str, defaults.send_offload_wait_mode); - io_srv_args.num_poll_offload_threads = - args.cast<size_t>(num_poll_offload_threads_str, defaults.num_poll_offload_threads); + io_srv_args.num_poll_offload_threads = args.cast<size_t>( + num_poll_offload_threads_str, defaults.num_poll_offload_threads); if (io_srv_args.num_poll_offload_threads == 0) { UHD_LOG_WARNING(LOG_ID, "Invalid value for num_poll_offload_threads. " @@ -75,7 +77,8 @@ io_service_args_t read_io_service_args( io_srv_args.num_poll_offload_threads = 1; } - auto read_thread_args = [&args](const std::regex& expr, std::map<size_t, size_t>& dest) { + auto read_thread_args = [&args]( + const std::regex& expr, std::map<size_t, size_t>& dest) { auto keys = args.keys(); for (const auto& key : keys) { std::smatch match; diff --git a/host/lib/usrp/common/io_service_mgr.cpp b/host/lib/usrp/common/io_service_mgr.cpp index 19c06a826..e30fa422d 100644 --- a/host/lib/usrp/common/io_service_mgr.cpp +++ b/host/lib/usrp/common/io_service_mgr.cpp @@ -40,8 +40,8 @@ namespace uhd { namespace usrp { class inline_io_service_mgr { public: - io_service::sptr connect_links(recv_link_if::sptr recv_link, - send_link_if::sptr send_link); + io_service::sptr connect_links( + recv_link_if::sptr recv_link, send_link_if::sptr send_link); void disconnect_links(recv_link_if::sptr recv_link, send_link_if::sptr send_link); @@ -56,8 +56,8 @@ private: std::map<link_pair_t, link_info_t> _link_info_map; }; -io_service::sptr inline_io_service_mgr::connect_links(recv_link_if::sptr recv_link, - send_link_if::sptr send_link) +io_service::sptr inline_io_service_mgr::connect_links( + recv_link_if::sptr recv_link, send_link_if::sptr send_link) { // Check if links are already connected const link_pair_t links{recv_link, send_link}; @@ -421,12 +421,7 @@ public: void disconnect_links(recv_link_if::sptr recv_link, send_link_if::sptr send_link); private: - enum io_service_type_t - { - INLINE_IO_SRV, - BLOCKING_IO_SRV, - POLLING_IO_SRV - }; + enum io_service_type_t { INLINE_IO_SRV, BLOCKING_IO_SRV, POLLING_IO_SRV }; struct xport_args_t { bool offload = false; @@ -463,7 +458,8 @@ io_service_mgr::sptr io_service_mgr::make(const uhd::device_addr_t& args) #ifdef HAVE_DPDK return std::make_shared<dpdk_io_service_mgr_impl>(); #else - UHD_LOG_WARNING(LOG_ID, "Cannot instantiate DPDK I/O service. Proceeding with regular I/O service."); + UHD_LOG_WARNING(LOG_ID, + "Cannot instantiate DPDK I/O service. Proceeding with regular I/O service."); #endif } return std::make_shared<io_service_mgr_impl>(args); @@ -485,8 +481,8 @@ io_service::sptr io_service_mgr_impl::connect_links(recv_link_if::sptr recv_link default_args.send_offload = false; } - const io_service_args_t args = read_io_service_args( - merge_io_service_dev_args(_args, stream_args), default_args); + const io_service_args_t args = + read_io_service_args(merge_io_service_dev_args(_args, stream_args), default_args); // Check if the links are already attached to an I/O service. If they are, // then use the same manager to connect, since links can only be connected @@ -528,7 +524,8 @@ io_service::sptr io_service_mgr_impl::connect_links(recv_link_if::sptr recv_link // the inline I/O service. Warn if a different one was requested. if (!_out_of_order_supported(recv_link, send_link)) { if (io_srv_type != INLINE_IO_SRV) { - UHD_LOG_WARNING(LOG_ID, "Link type does not support send/recv offload, ignoring"); + UHD_LOG_WARNING( + LOG_ID, "Link type does not support send/recv offload, ignoring"); } io_srv_type = INLINE_IO_SRV; } diff --git a/host/lib/usrp/common/lmx2592.cpp b/host/lib/usrp/common/lmx2592.cpp index e6ffdfbfb..e1c85c05f 100644 --- a/host/lib/usrp/common/lmx2592.cpp +++ b/host/lib/usrp/common/lmx2592.cpp @@ -80,12 +80,17 @@ enum intermediate_frequency_t { FRF_IN, }; -const char* log_intermediate_frequency(intermediate_frequency_t inter) { +const char* log_intermediate_frequency(intermediate_frequency_t inter) +{ switch (inter) { - case FRF_IN: return "FRF_IN"; - case FVCO: return "FVCO"; - case FLO: return "FLO"; - default: return "???"; + case FRF_IN: + return "FRF_IN"; + case FVCO: + return "FVCO"; + case FLO: + return "FLO"; + default: + return "???"; } } @@ -98,30 +103,30 @@ inline bool abs_less_than_compare(const double a, const double b) typedef std::pair<double, intermediate_frequency_t> offset_t; // comparator that uses absolute value on the first value of an offset_t -inline bool offset_abs_less_than_compare( - const offset_t a, - const offset_t b) +inline bool offset_abs_less_than_compare(const offset_t a, const offset_t b) { return std::abs(a.first) < std::abs(b.first); } -} +} // namespace -class lmx2592_impl : public lmx2592_iface { +class lmx2592_impl : public lmx2592_iface +{ public: explicit lmx2592_impl(write_spi_t write_fn, read_spi_t read_fn) : _write_fn([write_fn](const uint8_t addr, const uint16_t data) { - const uint32_t spi_transaction = - 0 | ((addr & SPI_ADDR_MASK) << SPI_ADDR_SHIFT) | data; - write_fn(spi_transaction); - }), - _read_fn([read_fn](const uint8_t addr) { - const uint32_t spi_transaction = - SPI_READ_FLAG | ((addr & SPI_ADDR_MASK) << SPI_ADDR_SHIFT); - return read_fn(spi_transaction); - }), - _regs(), - _rewrite_regs(true) { + const uint32_t spi_transaction = + 0 | ((addr & SPI_ADDR_MASK) << SPI_ADDR_SHIFT) | data; + write_fn(spi_transaction); + }) + , _read_fn([read_fn](const uint8_t addr) { + const uint32_t spi_transaction = SPI_READ_FLAG + | ((addr & SPI_ADDR_MASK) << SPI_ADDR_SHIFT); + return read_fn(spi_transaction); + }) + , _regs() + , _rewrite_regs(true) + { UHD_LOG_TRACE("LMX2592", "Initializing Synthesizer"); // Soft Reset @@ -133,16 +138,16 @@ public: _regs.reset = 0; // Set register values where driver defaults differ from the datasheet values - _regs.acal_enable = 0; - _regs.fcal_enable = 0; - _regs.cal_clk_div = 0; - _regs.vco_idac_ovr = 1; - _regs.cp_idn = 12; - _regs.cp_iup = 12; - _regs.vco_idac = 350; + _regs.acal_enable = 0; + _regs.fcal_enable = 0; + _regs.cal_clk_div = 0; + _regs.vco_idac_ovr = 1; + _regs.cp_idn = 12; + _regs.cp_iup = 12; + _regs.vco_idac = 350; _regs.mash_ditherer = 1; - _regs.outa_mux = lmx2592_regs_t::outa_mux_t::OUTA_MUX_VCO; - _regs.fcal_fast = 1; + _regs.outa_mux = lmx2592_regs_t::outa_mux_t::OUTA_MUX_VCO; + _regs.fcal_fast = 1; // Write default register values, ensures register copy is synchronized _rewrite_regs = true; @@ -152,13 +157,15 @@ public: commit(); } - ~lmx2592_impl() override { UHD_SAFE_CALL(_regs.powerdown = 1; commit();) } + ~lmx2592_impl() override + { + UHD_SAFE_CALL(_regs.powerdown = 1; commit();) + } - double set_frequency( - const double target_freq, + double set_frequency(const double target_freq, const bool spur_dodging = false, - const double spur_dodging_threshold = DEFAULT_LMX2592_SPUR_DODGING_THRESHOLD) - override + const double spur_dodging_threshold = + DEFAULT_LMX2592_SPUR_DODGING_THRESHOLD) override { // Enforce LMX frequency limits if (target_freq < LMX2592_MIN_OUT_FREQ or target_freq > LMX2592_MAX_OUT_FREQ) { @@ -187,7 +194,7 @@ public: const int vco_multiplier = target_freq > LMX2592_MAX_VCO_FREQ ? 2 : 1; const auto target_vco_freq = target_freq * output_divider; - const auto core_vco_freq = target_vco_freq / vco_multiplier; + const auto core_vco_freq = target_vco_freq / vco_multiplier; double input_freq = _ref_freq; @@ -205,18 +212,20 @@ public: input_freq /= _regs.pll_r_pre; // Multiplier - _regs.mult = narrow_cast<uint8_t>(std::floor(LMX2592_MAX_MULT_OUT_FREQ / input_freq)); + _regs.mult = + narrow_cast<uint8_t>(std::floor(LMX2592_MAX_MULT_OUT_FREQ / input_freq)); input_freq *= _regs.mult; // Post R divider - _regs.pll_r = narrow_cast<uint8_t>(std::ceil(input_freq / LMX2592_MAX_POSTR_DIV_OUT_FREQ)); + _regs.pll_r = + narrow_cast<uint8_t>(std::ceil(input_freq / LMX2592_MAX_POSTR_DIV_OUT_FREQ)); // Default to divide by 2, will be increased later if N exceeds its limit - int prescaler = 2; + int prescaler = 2; _regs.pll_n_pre = lmx2592_regs_t::pll_n_pre_t::PLL_N_PRE_DIVIDE_BY_2; const int min_n_divider = LMX2592_MIN_N_DIV[_regs.mash_order]; - double pfd_freq = input_freq / _regs.pll_r; + double pfd_freq = input_freq / _regs.pll_r; while (pfd_freq * (prescaler * min_n_divider) / vco_multiplier > core_vco_freq) { _regs.pll_r++; pfd_freq = input_freq / _regs.pll_r; @@ -224,7 +233,7 @@ public: // Calculate N and frac const auto N_dot_F = target_vco_freq / (pfd_freq * prescaler); - auto N = static_cast<uint16_t>(std::floor(N_dot_F)); + auto N = static_cast<uint16_t>(std::floor(N_dot_F)); if (N > MAX_N_DIVIDER) { _regs.pll_n_pre = lmx2592_regs_t::pll_n_pre_t::PLL_N_PRE_DIVIDE_BY_4; N /= 2; @@ -234,30 +243,37 @@ public: // Increase VCO step size to threshold to avoid primary fractional spurs const double min_vco_step_size = spur_dodging ? spur_dodging_threshold : 1; // Calculate Fden - const auto initial_fden = static_cast<uint32_t>(std::floor(pfd_freq * prescaler / min_vco_step_size)); + const auto initial_fden = + static_cast<uint32_t>(std::floor(pfd_freq * prescaler / min_vco_step_size)); const auto fden = (spur_dodging) ? _find_fden(initial_fden) : initial_fden; // Calculate Fnum const auto initial_fnum = static_cast<uint32_t>(std::round(frac * fden)); - const auto fnum = (spur_dodging) ? _find_fnum(N, initial_fnum, fden, prescaler, pfd_freq, output_divider, spur_dodging_threshold) : initial_fnum; + const auto fnum = (spur_dodging) ? _find_fnum(N, + initial_fnum, + fden, + prescaler, + pfd_freq, + output_divider, + spur_dodging_threshold) + : initial_fnum; // Calculate mash_seed // if spur_dodging is true, mash_seed is the first odd value less than fden // else mash_seed is int(fden / 2); - const uint32_t mash_seed = (spur_dodging) ? - _find_mash_seed(fden) : - static_cast<uint32_t>(fden / 2); + const uint32_t mash_seed = (spur_dodging) ? _find_mash_seed(fden) + : static_cast<uint32_t>(fden / 2); // Calculate actual Fcore_vco, Fvco, F_lo frequencies const auto actual_fvco = pfd_freq * prescaler * (N + double(fnum) / double(fden)); const auto actual_fcore_vco = actual_fvco / vco_multiplier; - const auto actual_f_lo = actual_fcore_vco * vco_multiplier / output_divider; + const auto actual_f_lo = actual_fcore_vco * vco_multiplier / output_divider; // Write to registers - _regs.pll_n = N; - _regs.pll_num_lsb = narrow_cast<uint16_t>(fnum); - _regs.pll_num_msb = narrow_cast<uint16_t>(fnum >> 16); - _regs.pll_den_lsb = narrow_cast<uint16_t>(fden); - _regs.pll_den_msb = narrow_cast<uint16_t>(fden >> 16); + _regs.pll_n = N; + _regs.pll_num_lsb = narrow_cast<uint16_t>(fnum); + _regs.pll_num_msb = narrow_cast<uint16_t>(fnum >> 16); + _regs.pll_den_lsb = narrow_cast<uint16_t>(fden); + _regs.pll_den_msb = narrow_cast<uint16_t>(fden >> 16); _regs.mash_seed_lsb = narrow_cast<uint16_t>(mash_seed); _regs.mash_seed_msb = narrow_cast<uint16_t>(mash_seed >> 16); @@ -276,7 +292,8 @@ public: return actual_f_lo; } - void set_mash_order(const mash_order_t mash_order) override { + void set_mash_order(const mash_order_t mash_order) override + { if (mash_order == mash_order_t::INT_N) { _regs.mash_order = lmx2592_regs_t::mash_order_t::MASH_ORDER_INT_MODE; @@ -294,22 +311,26 @@ public: } } - void set_reference_frequency(const double ref_freq) override { + void set_reference_frequency(const double ref_freq) override + { if (ref_freq < LMX2592_MIN_REF_FREQ or ref_freq > LMX2592_MAX_REF_FREQ) { - throw std::runtime_error("Reference frequency is out of bounds for the LMX2592"); + throw std::runtime_error( + "Reference frequency is out of bounds for the LMX2592"); } _ref_freq = ref_freq; } - void set_output_power(const output_t output, const unsigned int power) override { + void set_output_power(const output_t output, const unsigned int power) override + { UHD_LOGGER_TRACE("LMX2592") - << "Set output: " << (output == RF_OUTPUT_A ? "A" : "B") << " to power " << power; + << "Set output: " << (output == RF_OUTPUT_A ? "A" : "B") << " to power " + << power; const auto MAX_POWER = 63; if (power > MAX_POWER) { - UHD_LOGGER_ERROR("LMX2592") - << "Requested power level of " << power << " exceeds maximum of " << MAX_POWER; + UHD_LOGGER_ERROR("LMX2592") << "Requested power level of " << power + << " exceeds maximum of " << MAX_POWER; return; } @@ -322,9 +343,11 @@ public: commit(); } - void set_output_enable(const output_t output, const bool enable) override { - UHD_LOGGER_TRACE("LMX2592") << "Set output " << (output == RF_OUTPUT_A ? "A" : "B") - << " to " << (enable ? "On" : "Off"); + void set_output_enable(const output_t output, const bool enable) override + { + UHD_LOGGER_TRACE("LMX2592") + << "Set output " << (output == RF_OUTPUT_A ? "A" : "B") << " to " + << (enable ? "On" : "Off"); if (enable) { _regs.chdiv_dist_pd = 0; @@ -338,13 +361,13 @@ public: } else { if (output == RF_OUTPUT_A) { - _regs.outa_pd = 1; - _regs.vco_dista_pd = 1; + _regs.outa_pd = 1; + _regs.vco_dista_pd = 1; _regs.chdiv_dista_en = 0; } else { - _regs.outb_pd = 1; - _regs.vco_distb_pd = 1; + _regs.outb_pd = 1; + _regs.vco_distb_pd = 1; _regs.chdiv_distb_en = 0; } } @@ -357,40 +380,41 @@ public: commit(); } - bool get_lock_status() override { + bool get_lock_status() override + { // SPI MISO is being driven by lock detect // If the PLL is locked we expect to read 0xFFFF from any read, else 0x0000 - const auto value_read = _read_fn(_regs.ADDR_R0); + const auto value_read = _read_fn(_regs.ADDR_R0); const auto lock_status = (value_read == 0xFFFF); - UHD_LOG_TRACE( - "LMX2592", - str(boost::format("Read Lock status: 0x%04X") % static_cast<unsigned int>(value_read))); + UHD_LOG_TRACE("LMX2592", + str(boost::format("Read Lock status: 0x%04X") + % static_cast<unsigned int>(value_read))); return lock_status; } - void commit() override { + void commit() override + { UHD_LOGGER_DEBUG("LMX2592") << "Storing register cache " << (_rewrite_regs ? "completely" : "selectively") << " to LMX via SPI..."; - const auto changed_addrs = - _rewrite_regs ? _regs.get_all_addrs() : _regs.get_changed_addrs<size_t>(); + const auto changed_addrs = _rewrite_regs ? _regs.get_all_addrs() + : _regs.get_changed_addrs<size_t>(); for (const auto addr : changed_addrs) { _write_fn(addr, _regs.get_reg(addr)); UHD_LOGGER_TRACE("LMX2592") - << "Register " << std::setw(2) << static_cast<unsigned int>(addr) << ": 0x" - << std::hex << std::uppercase << std::setw(4) << std::setfill('0') - << static_cast<unsigned int>(_regs.get_reg(addr)); + << "Register " << std::setw(2) << static_cast<unsigned int>(addr) + << ": 0x" << std::hex << std::uppercase << std::setw(4) + << std::setfill('0') << static_cast<unsigned int>(_regs.get_reg(addr)); } _regs.save_state(); UHD_LOG_DEBUG("LMX2592", - "Writing registers complete: " - "Updated " - << changed_addrs.size() - << " registers."); + "Writing registers complete: " + "Updated " + << changed_addrs.size() << " registers."); _rewrite_regs = false; } @@ -407,8 +431,8 @@ private: // Members bool _rewrite_regs; double _ref_freq; - void _set_chdiv_values(const int output_divider_index) { - + void _set_chdiv_values(const int output_divider_index) + { // Configure divide segments and mux const auto seg1 = LMX2592_CHDIV_SEGS[output_divider_index][0]; const auto seg2 = LMX2592_CHDIV_SEGS[output_divider_index][1]; @@ -417,12 +441,13 @@ private: // Members _regs.chdiv_seg_sel = lmx2592_regs_t::chdiv_seg_sel_t::CHDIV_SEG_SEL_POWERDOWN; if (seg1 > 1) { - _regs.chdiv_seg_sel = lmx2592_regs_t::chdiv_seg_sel_t::CHDIV_SEG_SEL_DIV_SEG_1; + _regs.chdiv_seg_sel = + lmx2592_regs_t::chdiv_seg_sel_t::CHDIV_SEG_SEL_DIV_SEG_1; _regs.chdiv_seg1_en = 1; - _regs.outa_mux = lmx2592_regs_t::outa_mux_t::OUTA_MUX_DIVIDER; - _regs.outb_mux = lmx2592_regs_t::outb_mux_t::OUTB_MUX_DIVIDER; - _regs.vco_dista_pd = 1; - _regs.vco_distb_pd = 1; + _regs.outa_mux = lmx2592_regs_t::outa_mux_t::OUTA_MUX_DIVIDER; + _regs.outb_mux = lmx2592_regs_t::outb_mux_t::OUTB_MUX_DIVIDER; + _regs.vco_dista_pd = 1; + _regs.vco_distb_pd = 1; _regs.chdiv_dist_pd = 0; if (_regs.outa_pd == 0) { @@ -434,8 +459,8 @@ private: // Members } else { _regs.chdiv_seg1_en = 0; - _regs.outa_mux = lmx2592_regs_t::outa_mux_t::OUTA_MUX_VCO; - _regs.outb_mux = lmx2592_regs_t::outb_mux_t::OUTB_MUX_VCO; + _regs.outa_mux = lmx2592_regs_t::outa_mux_t::OUTA_MUX_VCO; + _regs.outb_mux = lmx2592_regs_t::outb_mux_t::OUTB_MUX_VCO; _regs.chdiv_dist_pd = 1; if (_regs.outa_pd == 0) { @@ -454,7 +479,8 @@ private: // Members if (seg2 > 1) { _regs.chdiv_seg2_en = 1; - _regs.chdiv_seg_sel = lmx2592_regs_t::chdiv_seg_sel_t::CHDIV_SEG_SEL_DIV_SEG_1_AND_2; + _regs.chdiv_seg_sel = + lmx2592_regs_t::chdiv_seg_sel_t::CHDIV_SEG_SEL_DIV_SEG_1_AND_2; } else { _regs.chdiv_seg2_en = 0; } @@ -473,7 +499,8 @@ private: // Members if (seg3 > 1) { _regs.chdiv_seg3_en = 1; - _regs.chdiv_seg_sel = lmx2592_regs_t::chdiv_seg_sel_t::CHDIV_SEG_SEL_DIV_SEG_1_2_AND_3; + _regs.chdiv_seg_sel = + lmx2592_regs_t::chdiv_seg_sel_t::CHDIV_SEG_SEL_DIV_SEG_1_2_AND_3; } else { _regs.chdiv_seg3_en = 0; } @@ -498,56 +525,33 @@ private: // Members int _get_k(const uint32_t fden) const { const auto mash = _regs.mash_order; - if (mash == lmx2592_regs_t::mash_order_t::MASH_ORDER_INT_MODE or - mash == lmx2592_regs_t::mash_order_t::MASH_ORDER_FIRST) - { + if (mash == lmx2592_regs_t::mash_order_t::MASH_ORDER_INT_MODE + or mash == lmx2592_regs_t::mash_order_t::MASH_ORDER_FIRST) { return 1; - } - else if (mash == lmx2592_regs_t::mash_order_t::MASH_ORDER_SECOND) - { - if (fden % 2 != 0) - { + } else if (mash == lmx2592_regs_t::mash_order_t::MASH_ORDER_SECOND) { + if (fden % 2 != 0) { return 1; - } - else { + } else { return 2; } - } - else if (mash == lmx2592_regs_t::mash_order_t::MASH_ORDER_THIRD) - { - if (fden % 2 != 0 and fden % 3 != 0) - { + } else if (mash == lmx2592_regs_t::mash_order_t::MASH_ORDER_THIRD) { + if (fden % 2 != 0 and fden % 3 != 0) { return 1; - } - else if (fden % 2 == 0 and fden % 3 != 0) - { + } else if (fden % 2 == 0 and fden % 3 != 0) { return 2; - } - else if (fden % 2 != 0 and fden % 3 == 0) - { + } else if (fden % 2 != 0 and fden % 3 == 0) { return 3; - } - else - { + } else { return 6; } - } - else if (mash == lmx2592_regs_t::mash_order_t::MASH_ORDER_FOURTH) - { - if (fden % 2 != 0 and fden % 3 != 0) - { + } else if (mash == lmx2592_regs_t::mash_order_t::MASH_ORDER_FOURTH) { + if (fden % 2 != 0 and fden % 3 != 0) { return 1; - } - else if (fden % 2 == 0 and fden % 3 != 0) - { + } else if (fden % 2 == 0 and fden % 3 != 0) { return 3; - } - else if (fden % 2 != 0 and fden % 3 == 0) - { + } else if (fden % 2 != 0 and fden % 3 == 0) { return 4; - } - else - { + } else { return 12; } } @@ -561,47 +565,38 @@ private: // Members auto fden = initial_fden; // mathematically, this loop should run a maximum of 4 times // i.e. initial_fden = 6N + 4 and mash_order is third or fourth order - for (int i = 0; i < 4; ++i) - { - if (_get_k(fden) == 1) - { - UHD_LOGGER_TRACE("LMX2592") << - "_find_fden(" << initial_fden << ") returned " << fden; + for (int i = 0; i < 4; ++i) { + if (_get_k(fden) == 1) { + UHD_LOGGER_TRACE("LMX2592") + << "_find_fden(" << initial_fden << ") returned " << fden; return fden; } // decrement rather than increment, as incrementing fden would decrease // the step size and violate any minimum step size that has been set --fden; } - UHD_LOGGER_WARNING("LMX2592") << - "Unable to find suitable fractional value denominator for spur dodging on LMX2592"; - UHD_LOGGER_ERROR("LMX2592") << - "Spur dodging failed"; + UHD_LOGGER_WARNING("LMX2592") << "Unable to find suitable fractional value " + "denominator for spur dodging on LMX2592"; + UHD_LOGGER_ERROR("LMX2592") << "Spur dodging failed"; return initial_fden; } // returns the offset of the closest multiple of // spur_frequency_base to target_frequency // A negative offset indicates the closest multiple is at a lower frequency - double _get_closest_spur_offset( - double target_frequency, - double spur_frequency_base) + double _get_closest_spur_offset(double target_frequency, double spur_frequency_base) { // find closest multiples of spur_frequency_base to target_frequency const auto first_harmonic_number = std::floor(target_frequency / spur_frequency_base); - const auto second_harmonic_number = - first_harmonic_number + 1; + const auto second_harmonic_number = first_harmonic_number + 1; // calculate offsets const auto first_spur_offset = (first_harmonic_number * spur_frequency_base) - target_frequency; const auto second_spur_offset = (second_harmonic_number * spur_frequency_base) - target_frequency; // select offset with smallest absolute value - return std::min({ - first_spur_offset, - second_spur_offset }, - abs_less_than_compare); + return std::min({first_spur_offset, second_spur_offset}, abs_less_than_compare); } // returns the closest spur offset among 4 different spurs @@ -611,8 +606,7 @@ private: // Members // 3. Reference to Fvco spur // 4. Reference to Flo spur // A negative offset indicates the closest spur is at a lower frequency - offset_t _get_min_offset_frequency( - const uint16_t N, + offset_t _get_min_offset_frequency(const uint16_t N, const uint32_t fnum, const uint32_t fden, const int prescaler, @@ -620,10 +614,10 @@ private: // Members const int output_divider) { // Calculate intermediate values - const auto fref = _ref_freq; + const auto fref = _ref_freq; const auto frf_in = pfd_freq * (N + double(fnum) / double(fden)); - const auto fvco = frf_in * prescaler; - const auto flo = fvco / output_divider; + const auto fvco = frf_in * prescaler; + const auto flo = fvco / output_divider; // the minimum offset is the smallest absolute value of these 4 values // as calculated by the _get_closest_spur_offset function @@ -631,23 +625,19 @@ private: // Members // in order to calculate the necessary frequency shift // Integer Boundary: - const offset_t ib_spur = { _get_closest_spur_offset(frf_in, pfd_freq), FRF_IN }; + const offset_t ib_spur = {_get_closest_spur_offset(frf_in, pfd_freq), FRF_IN}; // PFD Offset Spur: - const offset_t pfd_offset_spur = { _get_closest_spur_offset(fvco, pfd_freq), FVCO }; + const offset_t pfd_offset_spur = {_get_closest_spur_offset(fvco, pfd_freq), FVCO}; // Reference to Fvco Spur: - const offset_t fvco_spur = { _get_closest_spur_offset(fvco, fref), FVCO }; + const offset_t fvco_spur = {_get_closest_spur_offset(fvco, fref), FVCO}; // Reference to F_lo Spur: - const offset_t flo_spur = { _get_closest_spur_offset(flo, fref), FLO }; + const offset_t flo_spur = {_get_closest_spur_offset(flo, fref), FLO}; // use min with special comparator for minimal absolute value - return std::min({ - ib_spur, - pfd_offset_spur, - fvco_spur, - flo_spur}, + return std::min({ib_spur, pfd_offset_spur, fvco_spur, flo_spur}, offset_abs_less_than_compare); } @@ -659,8 +649,7 @@ private: // Members // PFD frequency will be at least 10x larger than the step size of // (fnum / fden). This function only considers at least 50% potential // values of fnum, and does not consider changes to N. - uint32_t _find_fnum( - const uint16_t N, + uint32_t _find_fnum(const uint16_t N, const uint32_t initial_fnum, const uint32_t fden, const int prescaler, @@ -669,40 +658,28 @@ private: // Members const double spur_dodging_threshold) { auto fnum = initial_fnum; - auto min_offset = _get_min_offset_frequency( - N, - fnum, - fden, - prescaler, - pfd_freq, - output_divider); - - UHD_LOGGER_TRACE("LMX2592") << - "closest spur is at " << min_offset.first << - " to " << log_intermediate_frequency(min_offset.second); + auto min_offset = + _get_min_offset_frequency(N, fnum, fden, prescaler, pfd_freq, output_divider); + + UHD_LOGGER_TRACE("LMX2592") << "closest spur is at " << min_offset.first << " to " + << log_intermediate_frequency(min_offset.second); // shift away from the closest integer boundary i.e. towards 0.5 const double delta_fnum_sign = ((((double)fnum) / ((double)fden)) < 0.5) ? 1 : -1; - while (std::abs(min_offset.first) < spur_dodging_threshold) - { + while (std::abs(min_offset.first) < spur_dodging_threshold) { double shift = spur_dodging_threshold; // if the spur is in the same direction as the desired shift direction... - if (std::signbit(min_offset.first) == std::signbit(delta_fnum_sign)) - { + if (std::signbit(min_offset.first) == std::signbit(delta_fnum_sign)) { shift += std::abs(min_offset.first); - } - else { + } else { shift -= std::abs(min_offset.first); } // convert shift of IF value to shift of Frf_in - if (min_offset.second == FVCO) - { + if (min_offset.second == FVCO) { shift /= prescaler; - } - else if (min_offset.second == FLO) - { + } else if (min_offset.second == FLO) { shift /= prescaler; shift *= output_divider; } @@ -710,33 +687,27 @@ private: // Members double delta_fnum_value = std::ceil((shift / pfd_freq) * fden); fnum += narrow_cast<int32_t>(delta_fnum_value * delta_fnum_sign); - UHD_LOGGER_TRACE("LMX2592") << - "adjusting fnum by " << (delta_fnum_value * delta_fnum_sign); + UHD_LOGGER_TRACE("LMX2592") + << "adjusting fnum by " << (delta_fnum_value * delta_fnum_sign); // fnum is unsigned, so this also checks for underflow - if (fnum >= fden) - { - UHD_LOGGER_WARNING("LMX2592") << - "Unable to find suitable fractional value numerator for spur dodging on LMX2592"; - UHD_LOGGER_ERROR("LMX2592") << - "Spur dodging failed"; + if (fnum >= fden) { + UHD_LOGGER_WARNING("LMX2592") + << "Unable to find suitable fractional value numerator for spur " + "dodging on LMX2592"; + UHD_LOGGER_ERROR("LMX2592") << "Spur dodging failed"; return initial_fnum; } min_offset = _get_min_offset_frequency( - N, - fnum, - fden, - prescaler, - pfd_freq, - output_divider); - - UHD_LOGGER_TRACE("LMX2592") << - "closest spur is at " << min_offset.first << - " to " << log_intermediate_frequency(min_offset.second); + N, fnum, fden, prescaler, pfd_freq, output_divider); + + UHD_LOGGER_TRACE("LMX2592") + << "closest spur is at " << min_offset.first << " to " + << log_intermediate_frequency(min_offset.second); } - UHD_LOGGER_TRACE("LMX2592") << - "_find_fnum(" << initial_fnum << ") returned " << fnum; + UHD_LOGGER_TRACE("LMX2592") + << "_find_fnum(" << initial_fnum << ") returned " << fnum; return fnum; } @@ -745,13 +716,13 @@ private: // Members { if (fden < 2) { return 1; - } - else { + } else { return (fden - 2) | 0x1; } }; }; -lmx2592_impl::sptr lmx2592_iface::make(write_spi_t write, read_spi_t read) { +lmx2592_impl::sptr lmx2592_iface::make(write_spi_t write, read_spi_t read) +{ return std::make_shared<lmx2592_impl>(write, read); } diff --git a/host/lib/usrp/common/recv_packet_demuxer.cpp b/host/lib/usrp/common/recv_packet_demuxer.cpp index 96eafa4be..c5ed1563e 100644 --- a/host/lib/usrp/common/recv_packet_demuxer.cpp +++ b/host/lib/usrp/common/recv_packet_demuxer.cpp @@ -5,15 +5,14 @@ // SPDX-License-Identifier: GPL-3.0-or-later // -#include <uhdlib/usrp/common/recv_packet_demuxer.hpp> -#include <uhd/utils/log.hpp> -#include <uhd/utils/byteswap.hpp> #include <uhd/transport/vrt_if_packet.hpp> #include <uhd/types/metadata.hpp> - +#include <uhd/utils/byteswap.hpp> +#include <uhd/utils/log.hpp> +#include <uhdlib/usrp/common/recv_packet_demuxer.hpp> #include <boost/thread/mutex.hpp> -#include <queue> #include <deque> +#include <queue> #include <vector> using namespace uhd; @@ -23,7 +22,9 @@ using namespace uhd::transport; struct recv_pkt_demux_mrb : public managed_recv_buffer { public: - recv_pkt_demux_mrb(void){/*NOP*/} + recv_pkt_demux_mrb(void) + { /*NOP*/ + } void release(void) { @@ -33,62 +34,68 @@ public: uint32_t buff[10]; }; -static UHD_INLINE uint32_t extract_sid(managed_recv_buffer::sptr &buff){ - //ASSUME that the data is in little endian format - return uhd::wtohx(buff->cast<const uint32_t *>()[1]); +static UHD_INLINE uint32_t extract_sid(managed_recv_buffer::sptr& buff) +{ + // ASSUME that the data is in little endian format + return uhd::wtohx(buff->cast<const uint32_t*>()[1]); } -recv_packet_demuxer::~recv_packet_demuxer(void){ +recv_packet_demuxer::~recv_packet_demuxer(void) +{ /* NOP */ } -class recv_packet_demuxer_impl : public uhd::usrp::recv_packet_demuxer{ +class recv_packet_demuxer_impl : public uhd::usrp::recv_packet_demuxer +{ public: - recv_packet_demuxer_impl( - transport::zero_copy_if::sptr transport, + recv_packet_demuxer_impl(transport::zero_copy_if::sptr transport, const size_t size, - const uint32_t sid_base - ): - _transport(transport), _sid_base(sid_base), _queues(size) + const uint32_t sid_base) + : _transport(transport), _sid_base(sid_base), _queues(size) { /* NOP */ } - managed_recv_buffer::sptr get_recv_buff(const size_t index, const double timeout){ + managed_recv_buffer::sptr get_recv_buff(const size_t index, const double timeout) + { boost::mutex::scoped_lock lock(_mutex); managed_recv_buffer::sptr buff; - //there is already an entry in the queue, so pop that - if (not _queues[index].wrapper.empty()){ + // there is already an entry in the queue, so pop that + if (not _queues[index].wrapper.empty()) { std::swap(buff, _queues[index].wrapper.front()); _queues[index].wrapper.pop(); return buff; } - while (true){ - //otherwise call into the transport + while (true) { + // otherwise call into the transport buff = _transport->get_recv_buff(timeout); - if (buff.get() == NULL) return buff; //timeout + if (buff.get() == NULL) + return buff; // timeout - //check the stream id to know which channel + // check the stream id to know which channel const size_t rx_index = extract_sid(buff) - _sid_base; - if (rx_index == index) return buff; //got expected message - - //otherwise queue and try again - if (rx_index < _queues.size()) _queues[rx_index].wrapper.push(buff); - else - { - UHD_LOGGER_ERROR("STREAMER") << "Got a data packet with unknown SID " << extract_sid(buff) ; - recv_pkt_demux_mrb *mrb = new recv_pkt_demux_mrb(); + if (rx_index == index) + return buff; // got expected message + + // otherwise queue and try again + if (rx_index < _queues.size()) + _queues[rx_index].wrapper.push(buff); + else { + UHD_LOGGER_ERROR("STREAMER") + << "Got a data packet with unknown SID " << extract_sid(buff); + recv_pkt_demux_mrb* mrb = new recv_pkt_demux_mrb(); vrt::if_packet_info_t info; - info.packet_type = vrt::if_packet_info_t::PACKET_TYPE_DATA; + info.packet_type = vrt::if_packet_info_t::PACKET_TYPE_DATA; info.num_payload_words32 = 1; - info.num_payload_bytes = info.num_payload_words32*sizeof(uint32_t); - info.has_sid = true; - info.sid = _sid_base + index; + info.num_payload_bytes = info.num_payload_words32 * sizeof(uint32_t); + info.has_sid = true; + info.sid = _sid_base + index; vrt::if_hdr_pack_le(mrb->buff, info); mrb->buff[info.num_header_words32] = rx_metadata_t::ERROR_CODE_OVERFLOW; - return mrb->make(mrb, mrb->buff, info.num_packet_words32*sizeof(uint32_t)); + return mrb->make( + mrb, mrb->buff, info.num_packet_words32 * sizeof(uint32_t)); } } } @@ -97,14 +104,17 @@ private: transport::zero_copy_if::sptr _transport; const uint32_t _sid_base; boost::mutex _mutex; - struct channel_guts_type{ - channel_guts_type(void): wrapper(container){} + struct channel_guts_type + { + channel_guts_type(void) : wrapper(container) {} std::deque<managed_recv_buffer::sptr> container; std::queue<managed_recv_buffer::sptr> wrapper; }; std::vector<channel_guts_type> _queues; }; -recv_packet_demuxer::sptr recv_packet_demuxer::make(transport::zero_copy_if::sptr transport, const size_t size, const uint32_t sid_base){ +recv_packet_demuxer::sptr recv_packet_demuxer::make( + transport::zero_copy_if::sptr transport, const size_t size, const uint32_t sid_base) +{ return sptr(new recv_packet_demuxer_impl(transport, size, sid_base)); } diff --git a/host/lib/usrp/common/validate_subdev_spec.cpp b/host/lib/usrp/common/validate_subdev_spec.cpp index 369119e4a..61895a7f8 100644 --- a/host/lib/usrp/common/validate_subdev_spec.cpp +++ b/host/lib/usrp/common/validate_subdev_spec.cpp @@ -5,58 +5,68 @@ // SPDX-License-Identifier: GPL-3.0-or-later // -#include <uhdlib/usrp/common/validate_subdev_spec.hpp> #include <uhd/exception.hpp> #include <uhd/utils/assert_has.hpp> +#include <uhdlib/usrp/common/validate_subdev_spec.hpp> #include <boost/format.hpp> using namespace uhd; using namespace uhd::usrp; -namespace uhd{ namespace usrp{ +namespace uhd { namespace usrp { - static std::ostream& operator<< (std::ostream &out, const subdev_spec_pair_t &pair){ - out << pair.db_name << ":" << pair.sd_name; - return out; - } +static std::ostream& operator<<(std::ostream& out, const subdev_spec_pair_t& pair) +{ + out << pair.db_name << ":" << pair.sd_name; + return out; +} + +}} // namespace uhd::usrp + +void uhd::usrp::validate_subdev_spec(property_tree::sptr tree, + const subdev_spec_t& spec, + const std::string& type, + const std::string& mb) +{ + const size_t num_dsps = + tree->list(str(boost::format("/mboards/%s/%s_dsps") % mb % type)).size(); + + // sanity checking on the length + if (spec.size() == 0) + throw uhd::value_error( + str(boost::format("Empty %s subdevice specification is not supported.\n") + % type)); + if (spec.size() > num_dsps) + throw uhd::value_error( + str(boost::format("The subdevice specification \"%s\" is too long.\n" + "The user specified %u channels, but there are only %u %s " + "dsps on mboard %s.\n") + % spec.to_string() % spec.size() % num_dsps % type % mb)); -}} - -void uhd::usrp::validate_subdev_spec( - property_tree::sptr tree, - const subdev_spec_t &spec, - const std::string &type, - const std::string &mb -){ - const size_t num_dsps = tree->list(str(boost::format("/mboards/%s/%s_dsps") % mb % type)).size(); - - //sanity checking on the length - if (spec.size() == 0) throw uhd::value_error(str(boost::format( - "Empty %s subdevice specification is not supported.\n" - ) % type)); - if (spec.size() > num_dsps) throw uhd::value_error(str(boost::format( - "The subdevice specification \"%s\" is too long.\n" - "The user specified %u channels, but there are only %u %s dsps on mboard %s.\n" - ) % spec.to_string() % spec.size() % num_dsps % type % mb)); - - //make a list of all possible specs + // make a list of all possible specs subdev_spec_t all_specs; - for(const std::string &db: tree->list(str(boost::format("/mboards/%s/dboards") % mb))){ - for(const std::string &sd: tree->list(str(boost::format("/mboards/%s/dboards/%s/%s_frontends") % mb % db % type))){ + for (const std::string& db : + tree->list(str(boost::format("/mboards/%s/dboards") % mb))) { + for (const std::string& sd : + tree->list(str( + boost::format("/mboards/%s/dboards/%s/%s_frontends") % mb % db % type))) { all_specs.push_back(subdev_spec_pair_t(db, sd)); } } - //validate that the spec is possible - for(const subdev_spec_pair_t &pair: spec){ - uhd::assert_has(all_specs, pair, str(boost::format("%s subdevice specification on mboard %s") % type % mb)); + // validate that the spec is possible + for (const subdev_spec_pair_t& pair : spec) { + uhd::assert_has(all_specs, + pair, + str(boost::format("%s subdevice specification on mboard %s") % type % mb)); } - //enable selected frontends, disable others - for(const subdev_spec_pair_t &pair: all_specs){ + // enable selected frontends, disable others + for (const subdev_spec_pair_t& pair : all_specs) { const bool enb = uhd::has(spec, pair); - tree->access<bool>(str(boost::format( - "/mboards/%s/dboards/%s/%s_frontends/%s/enabled" - ) % mb % pair.db_name % type % pair.sd_name)).set(enb); + tree->access<bool>( + str(boost::format("/mboards/%s/dboards/%s/%s_frontends/%s/enabled") % mb + % pair.db_name % type % pair.sd_name)) + .set(enb); } } |