diff options
Diffstat (limited to 'fpga/usrp3/top/x300/coregen/bootram/simulation/functional')
11 files changed, 0 insertions, 508 deletions
diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simcmds.tcl b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simcmds.tcl deleted file mode 100755 index 212a904f5..000000000 --- a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simcmds.tcl +++ /dev/null @@ -1,64 +0,0 @@ -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. - - - - - - - - -wcfg new -isim set radix hex -wave add /bootram_tb/status - wave add /bootram_tb/bootram_synth_inst/BMG_PORT/CLKA - wave add /bootram_tb/bootram_synth_inst/BMG_PORT/ADDRA - wave add /bootram_tb/bootram_synth_inst/BMG_PORT/DINA - wave add /bootram_tb/bootram_synth_inst/BMG_PORT/WEA - wave add /bootram_tb/bootram_synth_inst/BMG_PORT/ENA - wave add /bootram_tb/bootram_synth_inst/BMG_PORT/DOUTA -run all -quit diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_isim.sh b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_isim.sh deleted file mode 100755 index 0768d7b5f..000000000 --- a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_isim.sh +++ /dev/null @@ -1,71 +0,0 @@ -#!/bin/sh -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -#-------------------------------------------------------------------------------- - -cp ../../../bootram.mif . - - -echo "Compiling Core Verilog UNISIM/Behavioral model" -vlogcomp -work work ../../../bootram.v -vhpcomp -work work ../../example_design/bootram_exdes.vhd - -echo "Compiling Test Bench Files" - -vhpcomp -work work ../bmg_tb_pkg.vhd -vhpcomp -work work ../random.vhd -vhpcomp -work work ../data_gen.vhd -vhpcomp -work work ../addr_gen.vhd -vhpcomp -work work ../checker.vhd -vhpcomp -work work ../bmg_stim_gen.vhd -vhpcomp -work work ../bootram_synth.vhd -vhpcomp -work work ../bootram_tb.vhd - - -vlogcomp -work work $XILINX/verilog/src/glbl.v -fuse work.bootram_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o bootram_tb.exe - -./bootram_tb.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_mti.bat b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_mti.bat deleted file mode 100755 index 5964f52d7..000000000 --- a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_mti.bat +++ /dev/null @@ -1,3 +0,0 @@ -#-------------------------------------------------------------------------------- - -vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_mti.do b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_mti.do deleted file mode 100755 index ba3c8ef12..000000000 --- a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_mti.do +++ /dev/null @@ -1,77 +0,0 @@ -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -#-------------------------------------------------------------------------------- -cp ../../../bootram.mif . - vlib work -vmap work work - -echo "Compiling Core Verilog UNISIM/Behavioral model" -vlog -work work ../../../bootram.v -vcom -work work ../../example_design/bootram_exdes.vhd - -echo "Compiling Test Bench Files" - -vcom -work work ../bmg_tb_pkg.vhd -vcom -work work ../random.vhd -vcom -work work ../data_gen.vhd -vcom -work work ../addr_gen.vhd -vcom -work work ../checker.vhd -vcom -work work ../bmg_stim_gen.vhd -vcom -work work ../bootram_synth.vhd -vcom -work work ../bootram_tb.vhd - - -vlog -work work $env(XILINX)/verilog/src/glbl.v -vsim -novopt -t ps -L XilinxCoreLib_ver -L unisims_ver glbl work.bootram_tb - -#Disabled waveform to save the disk space -add log -r /* -#Ignore integer warnings at time 0 -set StdArithNoWarnings 1 -run 0 -set StdArithNoWarnings 0 - -run -all diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_mti.sh b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_mti.sh deleted file mode 100755 index 5964f52d7..000000000 --- a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_mti.sh +++ /dev/null @@ -1,3 +0,0 @@ -#-------------------------------------------------------------------------------- - -vsim -c -do simulate_mti.do diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_ncsim.sh b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_ncsim.sh deleted file mode 100755 index eabc07d61..000000000 --- a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_ncsim.sh +++ /dev/null @@ -1,72 +0,0 @@ -#!/bin/sh -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -#-------------------------------------------------------------------------------- -cp ../../../bootram.mif . - - -mkdir work -echo "Compiling Core Verilog UNISIM/Behavioral model" -ncvlog -work work ../../../bootram.v -ncvhdl -v93 -work work ../../example_design/bootram_exdes.vhd - -echo "Compiling Test Bench Files" - -ncvhdl -v93 -work work ../bmg_tb_pkg.vhd -ncvhdl -v93 -work work ../random.vhd -ncvhdl -v93 -work work ../data_gen.vhd -ncvhdl -v93 -work work ../addr_gen.vhd -ncvhdl -v93 -work work ../checker.vhd -ncvhdl -v93 -work work ../bmg_stim_gen.vhd -ncvhdl -v93 -work work ../bootram_synth.vhd -ncvhdl -v93 -work work ../bootram_tb.vhd - -echo "Elaborating Design" -ncvlog -work work $XILINX/verilog/src/glbl.v -ncelab -access +rwc glbl work.bootram_tb - -echo "Simulating Design" -ncsim -gui -input @"simvision -input wave_ncsim.sv" work.bootram_tb diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_vcs.sh b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_vcs.sh deleted file mode 100755 index 0eff1c3fe..000000000 --- a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/simulate_vcs.sh +++ /dev/null @@ -1,71 +0,0 @@ -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -#-------------------------------------------------------------------------------- -#!/bin/sh -cp ../../../bootram.mif . -rm -rf simv* csrc DVEfiles AN.DB - -echo "Compiling Core Verilog UNISIM/Behavioral model" -vlogan +v2k ../../../bootram.v -vhdlan ../../example_design/bootram_exdes.vhd - -echo "Compiling Test Bench Files" -vhdlan ../bmg_tb_pkg.vhd -vhdlan ../random.vhd -vhdlan ../data_gen.vhd -vhdlan ../addr_gen.vhd -vhdlan ../checker.vhd -vhdlan ../bmg_stim_gen.vhd -vhdlan ../bootram_synth.vhd -vhdlan ../bootram_tb.vhd - -echo "Elaborating Design" -vlogan +v2k $XILINX/verilog/src/glbl.v -vcs +vcs+lic+wait -debug bootram_tb glbl - -echo "Simulating Design" -./simv -ucli -i ucli_commands.key -dve -session vcs_session.tcl diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/ucli_commands.key b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/ucli_commands.key deleted file mode 100755 index 358a13b79..000000000 --- a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/ucli_commands.key +++ /dev/null @@ -1,4 +0,0 @@ -dump -file bmg_vcs.vpd -type VPD -dump -add bootram_tb -run -quit diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/vcs_session.tcl b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/vcs_session.tcl deleted file mode 100755 index b55991252..000000000 --- a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/vcs_session.tcl +++ /dev/null @@ -1,84 +0,0 @@ - - - - - - - - - -#-------------------------------------------------------------------------------- -#-- -#-- BMG core Demo Testbench -#-- -#-------------------------------------------------------------------------------- -# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of Xilinx, Inc. and is protected under U.S. and -# international copyright and other intellectual property -# laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# Xilinx, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) Xilinx shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or Xilinx had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# Xilinx products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of Xilinx products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# Filename: vcs_session.tcl -# -# Description: -# This is the VCS wave form file. -# -#-------------------------------------------------------------------------------- -if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } { - gui_open_db -design V1 -file bmg_vcs.vpd -nosource -} -gui_set_precision 1ps -gui_set_time_units 1ps - -gui_open_window Wave -gui_sg_create bootram_Group -gui_list_add_group -id Wave.1 {bootram_Group} - - gui_sg_addsignal -group bootram_Group /bootram_tb/status - gui_sg_addsignal -group bootram_Group /bootram_tb/bootram_synth_inst/bmg_port/CLKA - gui_sg_addsignal -group bootram_Group /bootram_tb/bootram_synth_inst/bmg_port/ADDRA - gui_sg_addsignal -group bootram_Group /bootram_tb/bootram_synth_inst/bmg_port/DINA - gui_sg_addsignal -group bootram_Group /bootram_tb/bootram_synth_inst/bmg_port/WEA - gui_sg_addsignal -group bootram_Group /bootram_tb/bootram_synth_inst/bmg_port/ENA - gui_sg_addsignal -group bootram_Group /bootram_tb/bootram_synth_inst/bmg_port/DOUTA - -gui_zoom -window Wave.1 -full diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/wave_mti.do b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/wave_mti.do deleted file mode 100755 index 13844e041..000000000 --- a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/wave_mti.do +++ /dev/null @@ -1,37 +0,0 @@ - - - - - - - - - -onerror {resume} -quietly WaveActivateNextPane {} 0 - - add wave -noupdate /bootram_tb/status - add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/CLKA - add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/ADDRA - add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/DINA - add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/WEA - add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/ENA - add wave -noupdate /bootram_tb/bootram_synth_inst/bmg_port/DOUTA - -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {0 ps} 0} -configure wave -namecolwidth 197 -configure wave -valuecolwidth 106 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ps -update -WaveRestoreZoom {0 ps} {9464063 ps} diff --git a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/wave_ncsim.sv b/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/wave_ncsim.sv deleted file mode 100755 index 6e51f9989..000000000 --- a/fpga/usrp3/top/x300/coregen/bootram/simulation/functional/wave_ncsim.sv +++ /dev/null @@ -1,22 +0,0 @@ - - - - - - - - - - -window new WaveWindow -name "Waves for BMG Example Design" -waveform using "Waves for BMG Example Design" - - waveform add -signals /bootram_tb/status - waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/CLKA - waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/ADDRA - waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/DINA - waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/WEA - waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/ENA - waveform add -signals /bootram_tb/bootram_synth_inst/bmg_port/DOUTA - -console submit -using simulator -wait no "run" |