diff options
Diffstat (limited to 'fpga/usrp3/top/x300/coregen/Makefile.srcs')
| -rw-r--r-- | fpga/usrp3/top/x300/coregen/Makefile.srcs | 95 |
1 files changed, 95 insertions, 0 deletions
diff --git a/fpga/usrp3/top/x300/coregen/Makefile.srcs b/fpga/usrp3/top/x300/coregen/Makefile.srcs new file mode 100644 index 000000000..d70c89260 --- /dev/null +++ b/fpga/usrp3/top/x300/coregen/Makefile.srcs @@ -0,0 +1,95 @@ +# +# Copyright 2012 Ettus Research LLC +# + +################################################## +# Coregen Sources +################################################## +CG_TMP_DIR = $(HOME)/.tmp/$(NAME)_coregen +CG_SOURCE_DIR = $(BASE_DIR)/x300/coregen +CG_BUILD_DIR = $(BUILD_DIR)/coregen + +COREGEN_SRCS = $(abspath $(addprefix $(CG_BUILD_DIR)/, \ +input_sample_fifo.v \ +input_sample_fifo.xco \ +axi64_8k_2clk_fifo.v \ +fifo_4k_2clk.v \ +radio_clk_gen.v \ +radio_clk_gen.xco \ +bus_clk_gen.v \ +bus_clk_gen.xco \ +pcie_clk_gen.v \ +pcie_clk_gen.xco \ +bootram.xco \ +)) + +COREGEN_DRAM_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \ +axi_intercon_2x64_128.xco \ +ddr3_32bit/user_design/rtl/ddr3_32bit.v \ +ddr3_32bit/user_design/constraints/ddr3_32bit.ucf \ +ddr3_32bit.xco \ +)) + +COREGEN_CHIPSCOPE_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \ +chipscope_ila.v \ +chipscope_ila.xco \ +chipscope_ila_64.v \ +chipscope_ila_64.xco \ +chipscope_icon.v \ +chipscope_icon.xco \ +chipscope_icon_2port.v \ +chipscope_icon_2port.xco \ +fifo_xlnx_16x40_2clk.v \ +fifo_xlnx_16x40_2clk.xco \ +fifo_short_2clk.v \ +fifo_short_2clk.xco \ +)) + +ONE_GIG_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \ +gige_sfp_mdio.v \ +gige_sfp_mdio/example_design/gige_sfp_mdio_block.v \ +gige_sfp_mdio/example_design/gige_sfp_mdio_reset_sync.v \ +gige_sfp_mdio/example_design/gige_sfp_mdio_sync_block.v \ +gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_transceiver.v \ +gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_gtwizard.v \ +gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_gtwizard_gt.v \ +gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_gtwizard_init.v \ +gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_tx_startup_fsm.v \ +gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_rx_startup_fsm.v \ +gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_recclk_monitor.v \ +gige_sfp.v \ +gige_sfp/example_design/gige_sfp_block.v \ +gige_sfp/example_design/gige_sfp_reset_sync.v \ +gige_sfp/example_design/gige_sfp_sync_block.v \ +gige_sfp/example_design/transceiver/gige_sfp_transceiver.v \ +gige_sfp/example_design/transceiver/gige_sfp_gtwizard.v \ +gige_sfp/example_design/transceiver/gige_sfp_gtwizard_gt.v \ +gige_sfp/example_design/transceiver/gige_sfp_gtwizard_init.v \ +gige_sfp/example_design/transceiver/gige_sfp_tx_startup_fsm.v \ +gige_sfp/example_design/transceiver/gige_sfp_rx_startup_fsm.v \ +)) + +TEN_GIG_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \ +ten_gig_eth_pcs_pma.v \ +ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.v \ +ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.ucf \ +ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_block.v \ +ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_mod.v \ +ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gt_usrclk_source.v \ +ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v \ +ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser.v \ +)) + +#make rule to regenerate bootram when the coe file is changed +#this takes place out of tree to make the coregen tool happy +$(CG_TMP_DIR)/bootram.coe: $(CG_SOURCE_DIR)/bootram.coe + mkdir -p $(CG_TMP_DIR) + cp -r $(CG_SOURCE_DIR)/* $(CG_TMP_DIR)/ + coregen -b $(CG_TMP_DIR)/bootram.xco -p $(CG_TMP_DIR) -r + +#copy all coregen products into the build dir +#these products will be deleted with make clean +$(COREGEN_SRCS): $(CG_TMP_DIR)/bootram.coe + mkdir -p $(CG_BUILD_DIR) + cp -r $(CG_SOURCE_DIR)/* $(CG_BUILD_DIR)/ + cp -r $(CG_TMP_DIR)/bootram.* $(CG_BUILD_DIR)/ |