diff options
Diffstat (limited to 'fpga/usrp3/lib/io_port2')
| -rw-r--r-- | fpga/usrp3/lib/io_port2/Makefile.srcs | 1 | ||||
| -rw-r--r-- | fpga/usrp3/lib/io_port2/pcie_basic_regs.v | 9 | ||||
| -rw-r--r-- | fpga/usrp3/lib/io_port2/pcie_dma_ctrl.v | 17 | ||||
| -rw-r--r-- | fpga/usrp3/lib/io_port2/pcie_lossy_samp_gate.v | 26 |
4 files changed, 43 insertions, 10 deletions
diff --git a/fpga/usrp3/lib/io_port2/Makefile.srcs b/fpga/usrp3/lib/io_port2/Makefile.srcs index 507b8895a..4ee23a7b4 100644 --- a/fpga/usrp3/lib/io_port2/Makefile.srcs +++ b/fpga/usrp3/lib/io_port2/Makefile.srcs @@ -16,4 +16,5 @@ IOPORT2_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/io_port2/, \ ./pcie_basic_regs.v \ ./pcie_dma_ctrl.v \ ./data_swapper_64.v \ +./pcie_lossy_samp_gate.v \ )) diff --git a/fpga/usrp3/lib/io_port2/pcie_basic_regs.v b/fpga/usrp3/lib/io_port2/pcie_basic_regs.v index e3790e81c..e360b6812 100644 --- a/fpga/usrp3/lib/io_port2/pcie_basic_regs.v +++ b/fpga/usrp3/lib/io_port2/pcie_basic_regs.v @@ -3,7 +3,10 @@ // -module pcie_basic_regs ( +module pcie_basic_regs #( + parameter SIGNATURE = 32'h0, + parameter CLK_FREQ = 32'h0 +) ( input clk, input reset, @@ -16,8 +19,8 @@ module pcie_basic_regs ( input [31:0] misc_status ); - localparam PCIE_FPGA_SIG_VAL = 32'h58333030; //X300 (ASCII) - localparam PCIE_FPGA_COUNTER_FREQ = 32'h0A6E49C0; //175MHz + localparam PCIE_FPGA_SIG_VAL = SIGNATURE; + localparam PCIE_FPGA_COUNTER_FREQ = CLK_FREQ; localparam PCIE_REG_ADDR_MASK = 20'h001FF; diff --git a/fpga/usrp3/lib/io_port2/pcie_dma_ctrl.v b/fpga/usrp3/lib/io_port2/pcie_dma_ctrl.v index 6809939af..9e0f05040 100644 --- a/fpga/usrp3/lib/io_port2/pcie_dma_ctrl.v +++ b/fpga/usrp3/lib/io_port2/pcie_dma_ctrl.v @@ -35,12 +35,14 @@ module pcie_dma_ctrl #( output rego_tvalid, input rego_tready, + output reg [NUM_STREAMS-1:0] set_enabled, output reg [NUM_STREAMS-1:0] set_clear, output [(NUM_STREAMS*FRAME_SIZE_W)-1:0] set_frame_size, output [(NUM_STREAMS*3)-1:0] swap_lanes, input [NUM_STREAMS-1:0] packet_stb, input [NUM_STREAMS-1:0] sample_stb, + input [NUM_STREAMS-1:0] stream_busy, input [NUM_STREAMS-1:0] stream_err, input [ROUTER_SID_W-1:0] rtr_sid, @@ -48,7 +50,7 @@ module pcie_dma_ctrl #( ); localparam DMA_REG_GRP_W = 4; - localparam DMA_CTRL_STATUS_REG = 4'h0; //[RW] R: Stream Error, W: Reset stream + localparam DMA_CTRL_STATUS_REG = 4'h0; //[RW] R: Stream Status, W: Stream Control localparam DMA_FSIZE_REG = 4'h4; //[RW] R: Frame Size, W: Frame Size localparam DMA_SAMP_CNT_REG = 4'h8; //[RW] R: Sample Count, W: Reset Count to 0 localparam DMA_PKT_CNT_REG = 4'hC; //[RW] R: Packet Count, W: Reset Count to 0 @@ -92,14 +94,15 @@ module pcie_dma_ctrl #( if (reset) begin frame_size_mem[i] <= DEFAULT_FSIZE; set_clear[i] <= 0; + set_enabled[i] <= 0; sw_buf_width_mem[i] <= 1; end else if (regi_tready & regi_tvalid & regi_wr) begin if (regi_addr == `GET_REG_OFFSET(DMA_CTRL_STATUS_REG, i)) begin - set_clear[i] <= regi_payload[0]; //DMA_CTRL_STATUS_REG[0] == Clear DMA queues + set_clear[i] <= regi_payload[0]; //DMA_CTRL_STATUS_REG[0] == Clear DMA queues + set_enabled[i] <= regi_payload[1]; //DMA_CTRL_STATUS_REG[1] == Enable DMA channel sw_buf_width_mem[i] <= regi_payload[4]; //DMA_CTRL_STATUS_REG[5:4] == SW Buffer Size (See note above) end else if (regi_addr == `GET_REG_OFFSET(DMA_FSIZE_REG, i)) begin frame_size_mem[i] <= regi_payload[FRAME_SIZE_W-1:0]; //DMA_FSIZE_REG[14:0] == DMA Frame size - set_clear[i] <= 1; end end else begin set_clear[i] <= 0; //set_clear should be "self-clearing" @@ -123,7 +126,7 @@ module pcie_dma_ctrl #( samp_count_mem[i] <= samp_count_mem[i] + 1; end end - end + end endgenerate //Readback @@ -131,14 +134,14 @@ module pcie_dma_ctrl #( (regi_addr[DMA_REG_GRP_W-1:0] == DMA_PKT_CNT_REG) ? pkt_count_mem[`EXTRACT_CHAN_NUM(regi_addr)] : ( (regi_addr[DMA_REG_GRP_W-1:0] == DMA_SAMP_CNT_REG) ? samp_count_mem[`EXTRACT_CHAN_NUM(regi_addr)] : ( (regi_addr[DMA_REG_GRP_W-1:0] == DMA_FSIZE_REG) ? frame_size_mem[`EXTRACT_CHAN_NUM(regi_addr)] : ( - (regi_addr[DMA_REG_GRP_W-1:0] == DMA_CTRL_STATUS_REG) ? {31'h0, stream_err[`EXTRACT_CHAN_NUM(regi_addr)]} : ( + (regi_addr[DMA_REG_GRP_W-1:0] == DMA_CTRL_STATUS_REG) ? {30'h0, stream_busy[`EXTRACT_CHAN_NUM(regi_addr)], stream_err[`EXTRACT_CHAN_NUM(regi_addr)]} : ( 32'hFFFFFFFF)))); assign rego_tvalid = regi_tvalid && regi_rd; assign regi_tready = rego_tready || (regi_tvalid && regi_wr); //Optional router - if (ENABLE_ROUTER == 1) begin + generate if (ENABLE_ROUTER == 1) begin pcie_pkt_route_specifier #( .BASE_ADDR((1<<ROUTER_SID_W) + REG_BASE_ADDR), .ADDR_MASK(20'hFFFFF^((1<<ROUTER_SID_W)-1)), .SID_WIDTH(ROUTER_SID_W), .DST_WIDTH(ROUTER_DST_W) @@ -147,7 +150,7 @@ module pcie_dma_ctrl #( .regi_tdata(regi_tdata), .regi_tvalid(regi_tvalid), .regi_tready(), .local_sid(rtr_sid), .fifo_dst(rtr_dst) ); - end + end endgenerate endmodule diff --git a/fpga/usrp3/lib/io_port2/pcie_lossy_samp_gate.v b/fpga/usrp3/lib/io_port2/pcie_lossy_samp_gate.v new file mode 100644 index 000000000..6f6b6377a --- /dev/null +++ b/fpga/usrp3/lib/io_port2/pcie_lossy_samp_gate.v @@ -0,0 +1,26 @@ +// +// Copyright 2013 Ettus Research LLC +// + + +module pcie_lossy_samp_gate +( + input [63:0] i_tdata, + input i_tvalid, + output i_tready, + + output [63:0] o_tdata, + output o_tvalid, + input o_tready, + + input drop, + output dropping +); + + assign o_tdata = i_tdata; + assign o_tvalid = i_tvalid & ~drop; + assign i_tready = o_tready | drop; + + assign dropping = drop & i_tvalid; + +endmodule // pcie_lossy_samp_gate |