diff options
Diffstat (limited to 'fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv')
| -rw-r--r-- | fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv b/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv index c3c71999d..3a434ceb0 100644 --- a/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv +++ b/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv @@ -27,17 +27,17 @@ module axi4s_fifo #( // Parameter Checks initial begin assert (i.DATA_WIDTH == o.DATA_WIDTH) else - $fatal("DATA_WIDTH mismatch"); + $fatal(1, "DATA_WIDTH mismatch"); assert (i.USER_WIDTH == o.USER_WIDTH) else - $fatal("USER_WIDTH mismatch"); + $fatal(1, "USER_WIDTH mismatch"); assert (i.TDATA == o.TDATA) else - $fatal("TDATA present mismatch"); + $fatal(1, "TDATA present mismatch"); assert (i.TUSER == o.TUSER) else - $fatal("TUSER present mismatch"); + $fatal(1, "TUSER present mismatch"); assert (i.TKEEP == o.TKEEP) else - $fatal("TKEEP present mismatch"); + $fatal(1, "TKEEP present mismatch"); assert (i.TLAST == o.TLAST) else - $fatal("TLAST present mismatch"); + $fatal(1, "TLAST present mismatch"); end AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH), |