diff options
Diffstat (limited to 'fpga/usrp2/top')
41 files changed, 6558 insertions, 0 deletions
diff --git a/fpga/usrp2/top/.gitignore b/fpga/usrp2/top/.gitignore new file mode 100644 index 000000000..0d90f1698 --- /dev/null +++ b/fpga/usrp2/top/.gitignore @@ -0,0 +1,2 @@ +/*.sav +build* diff --git a/fpga/usrp2/top/B100/.gitignore b/fpga/usrp2/top/B100/.gitignore new file mode 100644 index 000000000..1b2211df0 --- /dev/null +++ b/fpga/usrp2/top/B100/.gitignore @@ -0,0 +1 @@ +build* diff --git a/fpga/usrp2/top/B100/B100.ucf b/fpga/usrp2/top/B100/B100.ucf new file mode 100644 index 000000000..1c04c5d8d --- /dev/null +++ b/fpga/usrp2/top/B100/B100.ucf @@ -0,0 +1,204 @@ +## Main Clock +NET "CLK_FPGA_P" LOC = "R7" ; +NET "CLK_FPGA_N" LOC = "T7" ; + +## I2C +NET "SDA_FPGA" LOC = "T13" ; +NET "SCL_FPGA" LOC = "R13" ; + +## CGEN +NET "cgen_st_ld" LOC = "M13" ; +NET "cgen_st_refmon" LOC = "J14" ; +NET "cgen_st_status" LOC = "P6" ; +NET "cgen_ref_sel" LOC = "T2" ; +NET "cgen_sync_b" LOC = "H15" ; + +## FPGA Config +#NET "fpga_cfg_din" LOC = "T14" ; +#NET "fpga_cfg_cclk" LOC = "R14" ; +#NET "fpga_cfg_init_b" LOC = "T12" ; + +## MISC +#NET "mystery_bus<1>" LOC = "C4" ; +#NET "mystery_bus<0>" LOC = "E7" ; +NET "reset_n" LOC = "D5" ; +NET "PPS_IN" LOC = "M14" ; +NET "reset_codec" LOC = "B14" ; + +## recycles fpga_cfg_cclk for reset from fw +NET "ext_reset" LOC = "R14" ; + +## GPIF +NET "GPIF_D<15>" LOC = "P7" ; +NET "GPIF_D<14>" LOC = "N8" ; +NET "GPIF_D<13>" LOC = "T5" ; +NET "GPIF_D<12>" LOC = "T6" ; +NET "GPIF_D<11>" LOC = "N6" ; +NET "GPIF_D<10>" LOC = "P5" ; +NET "GPIF_D<9>" LOC = "R3" ; +NET "GPIF_D<8>" LOC = "T3" ; +NET "GPIF_D<7>" LOC = "N12" ; +NET "GPIF_D<6>" LOC = "P13" ; +NET "GPIF_D<5>" LOC = "P11" ; +NET "GPIF_D<4>" LOC = "R9" ; +NET "GPIF_D<3>" LOC = "T9" ; +NET "GPIF_D<2>" LOC = "N9" ; +NET "GPIF_D<1>" LOC = "P9" ; +NET "GPIF_D<0>" LOC = "P8" ; + +##NET "GPIF_CTL<3>" LOC = "N5" ; +NET "GPIF_CTL<3>" LOC = "P12" ; +NET "GPIF_CTL<2>" LOC = "M11" ; +NET "GPIF_CTL<1>" LOC = "M9" ; +NET "GPIF_CTL<0>" LOC = "M7" ; + +##NET "GPIF_RDY<3>" LOC = "N11" ; +##NET "GPIF_RDY<2>" LOC = "T10" ; +NET "GPIF_SLWR" LOC = "T4" ; +NET "GPIF_SLRD" LOC = "R5" ; + +##NET "GPIF_CS" LOC = "P12" ; +NET "GPIF_SLOE" LOC = "R11" ; +NET "GPIF_PKTEND" LOC = "P10" ; +NET "GPIF_ADR<0>" LOC = "T11" ; +NET "GPIF_ADR<1>" LOC = "H16" ; + +NET "IFCLK" LOC = "T8" ; + +## LEDs +NET "debug_led<2>" LOC = "R2" ; +NET "debug_led<1>" LOC = "N4" ; +NET "debug_led<0>" LOC = "P4" ; + +## Debug bus +NET "debug_clk<0>" LOC = "K15" ; +NET "debug_clk<1>" LOC = "K14" ; +NET "debug<0>" LOC = "K16" ; +NET "debug<1>" LOC = "J16" ; +NET "debug<2>" LOC = "C16" ; +NET "debug<3>" LOC = "C15" ; +NET "debug<4>" LOC = "E13" ; +NET "debug<5>" LOC = "D14" ; +NET "debug<6>" LOC = "D16" ; +NET "debug<7>" LOC = "D15" ; +NET "debug<8>" LOC = "E14" ; +NET "debug<9>" LOC = "F13" ; +NET "debug<10>" LOC = "G13" ; +NET "debug<11>" LOC = "F14" ; +NET "debug<12>" LOC = "E16" ; +NET "debug<13>" LOC = "F15" ; +NET "debug<14>" LOC = "H13" ; +NET "debug<15>" LOC = "G14" ; +NET "debug<16>" LOC = "G16" ; +NET "debug<17>" LOC = "F16" ; +NET "debug<18>" LOC = "J12" ; +NET "debug<19>" LOC = "J13" ; +NET "debug<20>" LOC = "L14" ; +NET "debug<21>" LOC = "L16" ; +NET "debug<22>" LOC = "M15" ; +NET "debug<23>" LOC = "M16" ; +NET "debug<24>" LOC = "L13" ; +NET "debug<25>" LOC = "K13" ; +NET "debug<26>" LOC = "P16" ; +NET "debug<27>" LOC = "N16" ; +NET "debug<28>" LOC = "R15" ; +NET "debug<29>" LOC = "P15" ; +NET "debug<30>" LOC = "N13" ; +NET "debug<31>" LOC = "N14" ; + +## ADC +NET "adc<11>" LOC = "B15" ; +NET "adc<10>" LOC = "A8" ; +NET "adc<9>" LOC = "B8" ; +NET "adc<8>" LOC = "C8" ; +NET "adc<7>" LOC = "D8" ; +NET "adc<6>" LOC = "C9" ; +NET "adc<5>" LOC = "A9" ; +NET "adc<4>" LOC = "C10" ; +NET "adc<3>" LOC = "D9" ; +NET "adc<2>" LOC = "A3" ; +NET "adc<1>" LOC = "B3" ; +NET "adc<0>" LOC = "A4" ; +NET "RXSYNC" LOC = "D10" ; + +## DAC +NET "TXBLANK" LOC = "K1" ; +NET "TXSYNC" LOC = "J2" ; +NET "dac<0>" LOC = "J1" ; +NET "dac<1>" LOC = "H3" ; +NET "dac<2>" LOC = "J3" ; +NET "dac<3>" LOC = "G2" ; +NET "dac<4>" LOC = "H1" ; +NET "dac<5>" LOC = "N3" ; +NET "dac<6>" LOC = "M4" ; +NET "dac<7>" LOC = "R1" ; +NET "dac<8>" LOC = "P2" ; +NET "dac<9>" LOC = "P1" ; +NET "dac<10>" LOC = "M1" ; +NET "dac<11>" LOC = "N1" ; +NET "dac<12>" LOC = "M3" ; +NET "dac<13>" LOC = "L4" ; + +## TX DB +NET "io_tx<0>" LOC = "K4" ; +NET "io_tx<1>" LOC = "L3" ; +NET "io_tx<2>" LOC = "L2" ; +NET "io_tx<3>" LOC = "F1" ; +NET "io_tx<4>" LOC = "F3" ; +NET "io_tx<5>" LOC = "G3" ; +NET "io_tx<6>" LOC = "E3" ; +NET "io_tx<7>" LOC = "E2" ; +NET "io_tx<8>" LOC = "E4" ; +NET "io_tx<9>" LOC = "F4" ; +NET "io_tx<10>" LOC = "D1" ; +NET "io_tx<11>" LOC = "E1" ; +NET "io_tx<12>" LOC = "D4" ; +NET "io_tx<13>" LOC = "D3" ; +NET "io_tx<14>" LOC = "C2" ; +NET "io_tx<15>" LOC = "C1" ; + +## RX DB +NET "io_rx<0>" LOC = "D7" ; +NET "io_rx<1>" LOC = "C6" ; +NET "io_rx<2>" LOC = "A6" ; +NET "io_rx<3>" LOC = "B6" ; +NET "io_rx<4>" LOC = "E9" ; +NET "io_rx<5>" LOC = "A7" ; +NET "io_rx<6>" LOC = "C7" ; +NET "io_rx<7>" LOC = "B10" ; +NET "io_rx<8>" LOC = "A10" ; +NET "io_rx<9>" LOC = "C11" ; +NET "io_rx<10>" LOC = "A11" ; +NET "io_rx<11>" LOC = "D11" ; +NET "io_rx<12>" LOC = "B12" ; +NET "io_rx<13>" LOC = "A12" ; +NET "io_rx<14>" LOC = "A14" ; +NET "io_rx<15>" LOC = "A13" ; + +## SPI +#NET "SEN_AUX" LOC = "C12" ; +#NET "SCLK_AUX" LOC = "D12" ; +#NET "MISO_AUX" LOC = "J5" ; +NET "SCLK_CODEC" LOC = "K3" ; +NET "SEN_CODEC" LOC = "D13" ; +NET "MOSI_CODEC" LOC = "C13" ; +NET "MISO_CODEC" LOC = "G4" ; + +NET "MISO_RX_DB" LOC = "E6" ; +NET "SEN_RX_DB" LOC = "B4" ; +NET "MOSI_RX_DB" LOC = "A5" ; +NET "SCLK_RX_DB" LOC = "C5" ; + +NET "MISO_TX_DB" LOC = "J4" ; +NET "SEN_TX_DB" LOC = "N2" ; +NET "MOSI_TX_DB" LOC = "L1" ; +NET "SCLK_TX_DB" LOC = "G1" ; + +## Dedicated pins +#NET "TMS" LOC = "B2" ; +#NET "TDO" LOC = "B16" ; +#NET "TDI" LOC = "B1" ; +#NET "TCK" LOC = "A15" ; + +#NET "fpga_cfg_prog_b" LOC = "A2" ; +#NET "fpga_cfg_done" LOC = "T15" ; diff --git a/fpga/usrp2/top/B100/B100.v b/fpga/usrp2/top/B100/B100.v new file mode 100644 index 000000000..cb4efa4fa --- /dev/null +++ b/fpga/usrp2/top/B100/B100.v @@ -0,0 +1,214 @@ +// +// Copyright 2011-2012 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module B100 + (input CLK_FPGA_P, input CLK_FPGA_N, // Diff + output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + + // GPIF + inout [15:0] GPIF_D, input [3:0] GPIF_CTL, output GPIF_SLOE, + output [1:0] GPIF_ADR, output GPIF_SLWR, output GPIF_SLRD, output GPIF_PKTEND, + input IFCLK, + + inout SDA_FPGA, inout SCL_FPGA, // I2C + + output SCLK_TX_DB, output SEN_TX_DB, output MOSI_TX_DB, input MISO_TX_DB, // DB TX SPI + output SCLK_RX_DB, output SEN_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, // DB TX SPI + output SCLK_CODEC, output SEN_CODEC, output MOSI_CODEC, input MISO_CODEC, // AD9862 main SPI + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, + + inout [15:0] io_tx, inout [15:0] io_rx, + + output [13:0] dac, output TXSYNC, output TXBLANK, + input [11:0] adc, input RXSYNC, + + input PPS_IN, + input reset_n, output reset_codec, + input ext_reset + ); + + assign reset_codec = 1; // Believed to be active low + + // ///////////////////////////////////////////////////////////////////////// + // Clocking + wire clk_fpga, clk_fpga_in, reset; + wire gpif_clk = IFCLK; + wire gpif_rst; + + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) + clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + + BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga)); + + reset_sync reset_sync(.clk(clk_fpga), .reset_in((~reset_n) | (~ext_reset)), .reset_out(reset)); + reset_sync reset_sync_gpif(.clk(gpif_clk), .reset_in((~reset_n) | (~ext_reset)), .reset_out(gpif_rst)); + + // ///////////////////////////////////////////////////////////////////////// + // SPI + wire mosi, sclk, miso; + assign { SCLK_TX_DB, MOSI_TX_DB } = ~SEN_TX_DB ? {sclk,mosi} : 2'b0; + assign { SCLK_RX_DB, MOSI_RX_DB } = ~SEN_RX_DB ? {sclk,mosi} : 2'b0; + assign { SCLK_CODEC, MOSI_CODEC } = ~SEN_CODEC ? {sclk,mosi} : 2'b0; + assign miso = (~SEN_TX_DB & MISO_TX_DB) | (~SEN_RX_DB & MISO_RX_DB) | + (~SEN_CODEC & MISO_CODEC); + + // ///////////////////////////////////////////////////////////////////////// + // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL + + assign TXBLANK = 0; + wire [13:0] tx_i, tx_q; + + genvar i; + generate + for(i=0;i<14;i=i+1) + begin : gen_dacout + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_inst (.Q(dac[i]), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(tx_i[i]), // 1-bit data input (associated with C0) + .D1(tx_q[i]), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + end // block: gen_dacout + endgenerate + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(1'b0), // 1-bit data input (associated with C0) + .D1(1'b1), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + + // ///////////////////////////////////////////////////////////////////////// + // RX ADC -- handles deinterleaving + + wire rxsync_0, rxsync_1; + reg [11:0] rx_i, rx_q; + wire [11:0] rx_a, rx_b; + + genvar j; + generate + for(j=0;j<12;j=j+1) + begin : gen_adcin + IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1 + .INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + IDDR2_inst (.Q0(rx_a[j]), // 1-bit output captured with C0 clock + .Q1(rx_b[j]), // 1-bit output captured with C1 clock + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D(adc[j]), // 1-bit DDR data input + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + end // block: gen_adcin + endgenerate + + IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1 + .INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + IDDR2_sync (.Q0(rxsync_0), // 1-bit output captured with C0 clock + .Q1(rxsync_1), // 1-bit output captured with C1 clock + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D(RXSYNC), // 1-bit DDR data input + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + + always @(posedge clk_fpga) + if(rxsync_0) + begin + rx_i <= rx_b; + rx_q <= rx_a; + end + else + begin + rx_i <= rx_a; + rx_q <= rx_b; + end + + // ///////////////////////////////////////////////////////////////////////// + // Main Core + wire [35:0] rx_data, tx_data, ctrl_data, resp_data; + wire rx_src_rdy, rx_dst_rdy, tx_src_rdy, tx_dst_rdy, resp_src_rdy, resp_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy; + wire dsp_rx_run, dsp_tx_run; + wire [7:0] sen8; + assign {SEN_CODEC,SEN_TX_DB,SEN_RX_DB} = sen8[2:0]; + wire [31:0] core_debug; + + assign debug_led = {dsp_tx_run, dsp_rx_run, cgen_st_ld}; + wire cgen_sync; + assign { cgen_sync_b, cgen_ref_sel } = {~cgen_sync, 1'b1}; + + u1plus_core #( + .NUM_RX_DSPS(1), + .DSP_RX_XTRA_FIFOSIZE(11), + .DSP_TX_XTRA_FIFOSIZE(12), + .USE_PACKET_PADDER(1) + ) core( + .clk(clk_fpga), .reset(reset), + .debug(core_debug), .debug_clk(debug_clk), + + .rx_data(rx_data), .rx_src_rdy(rx_src_rdy), .rx_dst_rdy(rx_dst_rdy), + .tx_data(tx_data), .tx_src_rdy(tx_src_rdy), .tx_dst_rdy(tx_dst_rdy), + .ctrl_data(ctrl_data), .ctrl_src_rdy(ctrl_src_rdy), .ctrl_dst_rdy(ctrl_dst_rdy), + .resp_data(resp_data), .resp_src_rdy(resp_src_rdy), .resp_dst_rdy(resp_dst_rdy), + + .dsp_rx_run(dsp_rx_run), .dsp_tx_run(dsp_tx_run), + .clock_sync(cgen_sync), + + .db_sda(SDA_FPGA), .db_scl(SCL_FPGA), + .sclk(sclk), .sen(sen8), .mosi(mosi), .miso(miso), + .io_tx(io_tx), .io_rx(io_rx), + .tx_i(tx_i), .tx_q(tx_q), + .rx_i(rx_i), .rx_q(rx_q), + .pps_in(PPS_IN) ); + + // ///////////////////////////////////////////////////////////////////////// + // Interface from host to/from GPIF + wire [31:0] gpif_debug; + slave_fifo slave_fifo (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_d(GPIF_D), + .gpif_ctl(GPIF_CTL), .sloe(GPIF_SLOE), .slwr(GPIF_SLWR), .slrd(GPIF_SLRD), + .pktend(GPIF_PKTEND), .fifoadr(GPIF_ADR), + + .fifo_clk(clk_fpga), .fifo_rst(reset), + .rx_data(rx_data), .rx_src_rdy(rx_src_rdy), .rx_dst_rdy(rx_dst_rdy), + .tx_data(tx_data), .tx_src_rdy(tx_src_rdy), .tx_dst_rdy(tx_dst_rdy), + .ctrl_data(ctrl_data), .ctrl_src_rdy(ctrl_src_rdy), .ctrl_dst_rdy(ctrl_dst_rdy), + .resp_data(resp_data), .resp_src_rdy(resp_src_rdy), .resp_dst_rdy(resp_dst_rdy), + + .debug(gpif_debug)); + + //assign debug = gpif_debug; + assign debug = core_debug; + +endmodule // B100 diff --git a/fpga/usrp2/top/B100/Makefile.B100 b/fpga/usrp2/top/B100/Makefile.B100 new file mode 100644 index 000000000..4687f2169 --- /dev/null +++ b/fpga/usrp2/top/B100/Makefile.B100 @@ -0,0 +1,106 @@ +# +# Copyright 2008-2012 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE := B100 +BUILD_DIR := build-B100/ + +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../gpif/Makefile.srcs + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan3A" \ +device XC3S1400A \ +package ft256 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +B100.v \ +u1plus_core.v \ +B100.ucf \ +timing.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ +$(GPIF_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto \ +"Verilog Macros" "$(CUSTOM_DEFS)" + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Generate Detailed MAP Report" TRUE \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/B100/core_compile b/fpga/usrp2/top/B100/core_compile new file mode 100755 index 000000000..2192bfa94 --- /dev/null +++ b/fpga/usrp2/top/B100/core_compile @@ -0,0 +1 @@ +iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac B100.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models diff --git a/fpga/usrp2/top/B100/timing.ucf b/fpga/usrp2/top/B100/timing.ucf new file mode 100644 index 000000000..c4404e1d0 --- /dev/null +++ b/fpga/usrp2/top/B100/timing.ucf @@ -0,0 +1,19 @@ +NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; +TIMESPEC "TS_CLK_FPGA_P" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; + +NET "IFCLK" TNM_NET = "IFCLK"; +TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20833 ps HIGH 50 %; + +#constrain FX2 IO +INST "GPIF_D<*>" TNM = gpif_net_in; +INST "GPIF_CTL<*>" TNM = gpif_net_in; + +INST "GPIF_D<*>" TNM = gpif_net_out; +INST "GPIF_ADR<*>" TNM = gpif_net_out; +INST "GPIF_SLWR" TNM = gpif_net_out; +INST "GPIF_SLOE" TNM = gpif_net_out; +INST "GPIF_SLRD" TNM = gpif_net_out; +INST "GPIF_PKTEND" TNM = gpif_net_out; + +TIMEGRP "gpif_net_in" OFFSET = IN 7 ns VALID 14 ns BEFORE "IFCLK" RISING; +TIMEGRP "gpif_net_out" OFFSET = OUT 7 ns AFTER "IFCLK" RISING; diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v new file mode 100644 index 000000000..9ffbaa202 --- /dev/null +++ b/fpga/usrp2/top/B100/u1plus_core.v @@ -0,0 +1,356 @@ +// +// Copyright 2011-2012 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + + +module u1plus_core +#( + parameter NUM_RX_DSPS = 2, + parameter CTRL_ACK_SID = 20, //needed for reply + + parameter DSP_TX_FIFOSIZE = 10, //4K MTU + parameter DSP_RX_FIFOSIZE = 10, //4K MTU + + parameter DSP_RX_XTRA_FIFOSIZE = 11, + parameter DSP_TX_XTRA_FIFOSIZE = 11, + + parameter USE_PACKET_PADDER = 0 +) + (input clk, input reset, + output [31:0] debug, output [1:0] debug_clk, + + // Host Interface + input [35:0] tx_data, input tx_src_rdy, output tx_dst_rdy, + output [35:0] rx_data, output rx_src_rdy, input rx_dst_rdy, + input [35:0] ctrl_data, input ctrl_src_rdy, output ctrl_dst_rdy, + output [35:0] resp_data, output resp_src_rdy, input resp_dst_rdy, + + output dsp_rx_run, output dsp_tx_run, output clock_sync, + + inout db_sda, inout db_scl, + output sclk, output [7:0] sen, output mosi, input miso, + + inout [15:0] io_tx, inout [15:0] io_rx, + output [13:0] tx_i, output [13:0] tx_q, + input [11:0] rx_i, input [11:0] rx_q, + input pps_in + ); + + localparam SR_MISC = 0; // 5 + localparam SR_USER_REGS = 5; // 2 + localparam SR_PADDER = 10; // 2 + + localparam SR_TX_CTRL = 32; // 6 + localparam SR_TX_DSP = 40; // 5 + localparam SR_TX_FE = 48; // 5 + + localparam SR_RX_CTRL0 = 96; // 9 + localparam SR_RX_DSP0 = 106; // 7 + localparam SR_RX_FE = 114; // 5 + + localparam SR_RX_CTRL1 = 128; // 9 + localparam SR_RX_DSP1 = 138; // 7 + + localparam SR_TIME64 = 192; // 6 + localparam SR_SPI = 208; // 3 + localparam SR_I2C = 216; // 1 + localparam SR_GPIO = 224; // 5 + + //compatibility number -> increment when the fpga has been sufficiently altered + localparam compat_num = {16'd11, 16'd0}; //major, minor + + //assign run signals used for ATR logic + wire [NUM_RX_DSPS-1:0] run_rx_n; + wire run_tx; + wire run_rx = |(run_rx_n); + assign dsp_rx_run = run_rx; + assign dsp_tx_run = run_tx; + + //shared time core signals + wire [63:0] vita_time, vita_time_pps; + + //shared settings bus signals + wire set_stb, set_stb_user; + wire [31:0] set_data, set_data_user; + wire [7:0] set_addr, set_addr_user; + + //shared SPI core signals + wire [31:0] spi_readback; + wire spi_ready; + + //shared I2C core signals + wire [31:0] i2c_readback; + wire i2c_ready; + + //shared GPIO core signals + wire [31:0] gpio_readback; + + /////////////////////////////////////////////////////////////////////////// + // Misc Registers - persistent across resets + /////////////////////////////////////////////////////////////////////////// + wire [31:0] config_word0; + setting_reg #(.my_addr(SR_MISC+0), .width(32)) sr_misc_config0 + (.clk(clk), .rst(1'b0/*reset*/), .strobe(set_stb), .addr(set_addr), .in(set_data), .out(config_word0)); + + wire [31:0] config_word1; + setting_reg #(.my_addr(SR_MISC+1), .width(32)) sr_misc_config1 + (.clk(clk), .rst(1'b0/*reset*/), .strobe(set_stb), .addr(set_addr), .in(set_data), .out(config_word1)); + + wire clock_sync_inv, clock_sync_enb; + setting_reg #(.my_addr(SR_MISC+2), .width(2)) sr_misc_clock_sync + (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data), + .out({clock_sync_inv, clock_sync_enb})); + + /////////////////////////////////////////////////////////////////////////// + // Settings Bus and Readback + /////////////////////////////////////////////////////////////////////////// + user_settings #(.BASE(SR_USER_REGS)) user_settings + (.clk(clk),.rst(reset), + .set_stb(set_stb), .set_addr(set_addr),.set_data(set_data), + .set_addr_user(set_addr_user),.set_data_user(set_data_user), .set_stb_user(set_stb_user) ); + + wire [35:0] ctrl_out_data, ctrl_int_data; + wire ctrl_out_src_rdy, ctrl_out_dst_rdy; + wire ctrl_int_src_rdy, ctrl_int_dst_rdy; + + fifo_cascade #(.WIDTH(36), .SIZE(9)) ctrl_fifo + (.clk(clk), .reset(reset), .clear(1'b0), + .datain(ctrl_data), .src_rdy_i(ctrl_src_rdy), .dst_rdy_o(ctrl_dst_rdy), .space(), + .dataout(ctrl_int_data), .src_rdy_o(ctrl_int_src_rdy), .dst_rdy_i(ctrl_int_dst_rdy), .occupied()); + + wire [31:0] num_rx_dsps_rb = NUM_RX_DSPS; + + wire [31:0] sfc_debug; + settings_fifo_ctrl #(.PROT_HDR(0), .ACK_SID(CTRL_ACK_SID), .XPORT_HDR(0)) sfc + ( + .clock(clk), .reset(reset), .clear(1'b0), + .vita_time(vita_time), .perfs_ready(spi_ready & i2c_ready), + .in_data(ctrl_int_data), .in_valid(ctrl_int_src_rdy), .in_ready(ctrl_int_dst_rdy), + .out_data(ctrl_out_data), .out_valid(ctrl_out_src_rdy), .out_ready(ctrl_out_dst_rdy), + .strobe(set_stb), .addr(set_addr), .data(set_data), + .word00(spi_readback),.word01(compat_num),.word02(i2c_readback),.word03(gpio_readback), + .word04(config_word0),.word05(config_word1),.word06(num_rx_dsps_rb),.word07(32'hffff_ffff), + .word08(32'hffff_ffff),.word09(32'hffff_ffff),.word10(vita_time[63:32]), + .word11(vita_time[31:0]),.word12(32'hffff_ffff),.word13(32'hffff_ffff), + .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]), + .debug(sfc_debug) + ); + + /////////////////////////////////////////////////////////////////////////// + // Time Core + /////////////////////////////////////////////////////////////////////////// + time_64bit #(.BASE(SR_TIME64)) time_64bit + (.clk(clk), .rst(reset), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), + .exp_time_in(0)); + + assign clock_sync = (clock_sync_enb)? (pps_in ^ clock_sync_inv) : 1'b0; + + /////////////////////////////////////////////////////////////////////////// + // SPI Core + /////////////////////////////////////////////////////////////////////////// + simple_spi_core #(.BASE(SR_SPI), .WIDTH(8), .CLK_IDLE(0), .SEN_IDLE(8'hff)) + simple_spi_core (.clock(clk), .reset(reset), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .readback(spi_readback), .ready(spi_ready), + .sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso)); + + /////////////////////////////////////////////////////////////////////////// + // I2C Core + /////////////////////////////////////////////////////////////////////////// + wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o; + simple_i2c_core #(.BASE(SR_I2C)) i2c_core + (.clock(clk),.reset(reset), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .readback(i2c_readback), .ready(i2c_ready), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o)); + + /////////////////////////////////////////////////////////////////////////// + // GPIO Core + /////////////////////////////////////////////////////////////////////////// + gpio_atr #(.BASE(SR_GPIO), .WIDTH(32)) + gpio_atr(.clk(clk),.reset(reset), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .rx(run_rx), .tx(run_tx), .gpio({io_tx, io_rx}), .gpio_readback(gpio_readback) ); + + // ///////////////////////////////////////////////////////////////////////// + // RX ADC Frontend, does IQ Balance, DC Offset, muxing + + wire [23:0] rx_fe_i, rx_fe_q; // 24 bits is total overkill here, but it matches u2/u2p + + rx_frontend #(.BASE(SR_RX_FE)) rx_frontend + (.clk(clk),.rst(reset), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a({rx_i,4'b00}),.adc_ovf_a(0), + .adc_b({rx_q,4'b00}),.adc_ovf_b(0), + .i_out(rx_fe_i), .q_out(rx_fe_q), .run(run_rx), .debug()); + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX * + + wire [35:0] rx_int2_data [NUM_RX_DSPS-1:0]; + wire rx_int2_src_rdy [NUM_RX_DSPS-1:0]; + wire rx_int2_dst_rdy [NUM_RX_DSPS-1:0]; + + genvar dspno; + generate + for(dspno = 0; dspno < NUM_RX_DSPS; dspno = dspno + 1) begin:gen_rx_dsps + + wire [31:0] sample_rx; + wire strobe_rx, clear_rx; + wire [35:0] vita_rx_data; + wire vita_rx_src_rdy, vita_rx_dst_rdy; + wire [35:0] int_rx_data; + wire int_rx_src_rdy, int_rx_dst_rdy; + + ddc_chain #(.BASE(SR_RX_DSP0+dspno*32), .DSPNO(dspno)) ddc_chain + (.clk(clk), .rst(reset), .clr(clear_rx), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), + .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q), + .sample(sample_rx), .run(run_rx_n[dspno]), .strobe(strobe_rx), + .debug() ); + + vita_rx_chain #(.BASE(SR_RX_CTRL0+dspno*32), .UNIT(dspno), .FIFOSIZE(DSP_RX_FIFOSIZE), .PROT_ENG_FLAGS(0), .DSP_NUMBER(dspno)) vita_rx_chain + (.clk(clk),.reset(reset), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), + .vita_time(vita_time), .overrun(), + .sample(sample_rx), .run(run_rx_n[dspno]), .strobe(strobe_rx), .clear_o(clear_rx), + .rx_data_o(vita_rx_data), .rx_dst_rdy_i(vita_rx_dst_rdy), .rx_src_rdy_o(vita_rx_src_rdy), + .debug() ); + + fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE+1)) rx_data_fifo + (.clk(clk), .reset(reset), .clear(1'b0), + .datain(vita_rx_data), .src_rdy_i(vita_rx_src_rdy), .dst_rdy_o(vita_rx_dst_rdy), .space(), + .dataout(int_rx_data), .src_rdy_o(int_rx_src_rdy), .dst_rdy_i(int_rx_dst_rdy), .occupied()); + + if (dspno == 0) begin + assign rx_int2_data[dspno] = int_rx_data; + assign rx_int2_src_rdy[dspno] = int_rx_src_rdy; + assign int_rx_dst_rdy = rx_int2_dst_rdy[dspno]; + end + else begin + fifo36_mux #(.prio(0)) // No priority, fair sharing + combine_rx_dsps ( + .clk(clk), .reset(reset), .clear(1'b0/*noclear*/), + .data0_i(rx_int2_data[dspno-1]), .src0_rdy_i(rx_int2_src_rdy[dspno-1]), .dst0_rdy_o(rx_int2_dst_rdy[dspno-1]), + .data1_i(int_rx_data), .src1_rdy_i(int_rx_src_rdy), .dst1_rdy_o(int_rx_dst_rdy), + .data_o(rx_int2_data[dspno]), .src_rdy_o(rx_int2_src_rdy[dspno]), .dst_rdy_i(rx_int2_dst_rdy[dspno]) + ); + end + + end + endgenerate + + // ///////////////////////////////////////////////////////////////////////// + // RX Stream muxing + + wire [35:0] rx_int3_data; + wire rx_int3_src_rdy, rx_int3_dst_rdy; + + fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_XTRA_FIFOSIZE)) rx_data_fifo_combined + (.clk(clk), .reset(reset), .clear(1'b0), + .datain(rx_int2_data[NUM_RX_DSPS-1]), .src_rdy_i(rx_int2_src_rdy[NUM_RX_DSPS-1]), .dst_rdy_o(rx_int2_dst_rdy[NUM_RX_DSPS-1]), .space(), + .dataout(rx_int3_data), .src_rdy_o(rx_int3_src_rdy), .dst_rdy_i(rx_int3_dst_rdy), .occupied()); + + generate + if (USE_PACKET_PADDER) begin + packet_padder36 #(.BASE(SR_PADDER)) packet_padder_rx_data36( + .clk(clk), .reset(reset), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .data_i(rx_int3_data), .src_rdy_i(rx_int3_src_rdy), .dst_rdy_o(rx_int3_dst_rdy), + .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy), + .always_flush(~dsp_rx_run)); + end + else begin + assign rx_data = rx_int3_data; + assign rx_src_rdy = rx_int3_src_rdy; + assign rx_int3_dst_rdy = rx_dst_rdy; + end + endgenerate + + /////////////////////////////////////////////////////////////////////////// + // MUX for TX async and resp data + /////////////////////////////////////////////////////////////////////////// + wire [35:0] tx_err_data, resp_data_int; + wire tx_err_src_rdy, resp_src_rdy_int; + wire tx_err_dst_rdy, resp_dst_rdy_int; + + fifo36_mux #(.prio(0)) // No priority, fair sharing + combine_async_and_resp ( + .clk(clk), .reset(reset), .clear(1'b0/*noclear*/), + .data0_i(ctrl_out_data), .src0_rdy_i(ctrl_out_src_rdy), .dst0_rdy_o(ctrl_out_dst_rdy), + .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), + .data_o(resp_data_int), .src_rdy_o(resp_src_rdy_int), .dst_rdy_i(resp_dst_rdy_int) + ); + + fifo_cascade #(.WIDTH(36), .SIZE(9)) resp_fifo + (.clk(clk), .reset(reset), .clear(1'b0), + .datain(resp_data_int), .src_rdy_i(resp_src_rdy_int), .dst_rdy_o(resp_dst_rdy_int), .space(), + .dataout(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy), .occupied()); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [23:0] tx_fe_i, tx_fe_q; + wire [31:0] sample_tx; + wire strobe_tx, clear_tx; + + vita_tx_chain #(.BASE(SR_TX_CTRL), + .FIFOSIZE(DSP_TX_FIFOSIZE), + .POST_ENGINE_FIFOSIZE(DSP_TX_XTRA_FIFOSIZE), + .REPORT_ERROR(1), .DO_FLOW_CONTROL(0), + .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0), + .DSP_NUMBER(0)) + vita_tx_chain + (.clk(clk), .reset(reset), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), + .sample(sample_tx), .strobe(strobe_tx), + .underrun(), .run(run_tx), .clear_o(clear_tx), + .debug()); + + duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain + (.clk(clk), .rst(reset), .clr(clear_tx), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), + .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .debug() ); + + tx_frontend #(.BASE(SR_TX_FE), .WIDTH_OUT(14)) tx_frontend + (.clk(clk), .rst(reset), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(1'b1), + .dac_a(tx_i), .dac_b(tx_q)); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Debug circuitry + + assign debug_clk = 2'b11; + assign debug = 32'hffffffff; + +endmodule // u1plus_core diff --git a/fpga/usrp2/top/E1x0/.gitignore b/fpga/usrp2/top/E1x0/.gitignore new file mode 100644 index 000000000..8d872713e --- /dev/null +++ b/fpga/usrp2/top/E1x0/.gitignore @@ -0,0 +1,6 @@ +*~ +build +*.log +*.cmd +tb_u1e +*.lxt diff --git a/fpga/usrp2/top/E1x0/E1x0.ucf b/fpga/usrp2/top/E1x0/E1x0.ucf new file mode 100644 index 000000000..278fc289a --- /dev/null +++ b/fpga/usrp2/top/E1x0/E1x0.ucf @@ -0,0 +1,261 @@ + +NET "CLK_FPGA_P" LOC = "Y11" ; +NET "CLK_FPGA_N" LOC = "Y10" ; + +## GPMC +NET "EM_D<15>" LOC = "D13" ; +NET "EM_D<14>" LOC = "D15" ; +NET "EM_D<13>" LOC = "C16" ; +NET "EM_D<12>" LOC = "B20" ; +NET "EM_D<11>" LOC = "A19" ; +NET "EM_D<10>" LOC = "A17" ; +NET "EM_D<9>" LOC = "E15" ; +NET "EM_D<8>" LOC = "F15" ; +NET "EM_D<7>" LOC = "E16" ; +NET "EM_D<6>" LOC = "F16" ; +NET "EM_D<5>" LOC = "B17" ; +NET "EM_D<4>" LOC = "C17" ; +NET "EM_D<3>" LOC = "B19" ; +NET "EM_D<2>" LOC = "D19" ; +NET "EM_D<1>" LOC = "C19" ; +NET "EM_D<0>" LOC = "A20" ; + +NET "EM_A<10>" LOC = "C14" ; +NET "EM_A<9>" LOC = "C10" ; +NET "EM_A<8>" LOC = "C5" ; +NET "EM_A<7>" LOC = "A18" ; +NET "EM_A<6>" LOC = "A15" ; +NET "EM_A<5>" LOC = "A12" ; +NET "EM_A<4>" LOC = "A10" ; +NET "EM_A<3>" LOC = "E7" ; +NET "EM_A<2>" LOC = "A7" ; +NET "EM_A<1>" LOC = "C15" ; + +NET "EM_NCS6" LOC = "E17" ; +NET "EM_NCS5" LOC = "E10" ; +NET "EM_NCS4" LOC = "E6" ; +#NET "EM_NCS1" LOC = "D18" ; +#NET "EM_NCS0" LOC = "D17" ; + +NET "EM_CLK" LOC = "F11" ; +NET "EM_WAIT0" LOC = "F14" ; +NET "EM_NBE<1>" LOC = "D14" ; +NET "EM_NBE<0>" LOC = "A13" ; +NET "EM_NWE" LOC = "B13" ; +NET "EM_NOE" LOC = "A14" ; +#NET "EM_NADV_ALE" LOC = "B15" ; +#NET "EM_NWP" LOC = "F13" ; + +## Overo GPIO +NET "overo_gpio0" LOC = "F9" ; # MISC GPIO for debug +NET "overo_gpio14" LOC = "C4" ; # MISC GPIO for debug +NET "overo_gpio21" LOC = "D5" ; # MISC GPIO for debug +NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug +NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug +NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug +NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug + +NET "overo_gpio127" LOC = "C8" ; # Changed name to gpio10 +NET "overo_gpio128" LOC = "G8" ; # Changed name to gpio186 + +NET "overo_gpio144" LOC = "A5" ; # tx_have_space +NET "overo_gpio145" LOC = "C7" ; # tx_underrun +NET "overo_gpio146" LOC = "A6" ; # rx_have_data +NET "overo_gpio147" LOC = "B6" ; # rx_overrun +NET "overo_gpio163" LOC = "D7" ; # MISC GPIO for debug +NET "overo_gpio170" LOC = "E8" ; # MISC GPIO for debug +NET "overo_gpio176" LOC = "B4" ; # MISC GPIO for debug + +## Overo UART +NET "overo_txd1" LOC = "C6" ; +NET "overo_rxd1" LOC = "D6" ; +NET "fpga_txd1" LOC = "AB9" ; +NET "fpga_rxd1" LOC = "AB8" ; + +## FTDI UART to USB converter +NET "FPGA_TXD" LOC = "G19" ; +NET "FPGA_RXD" LOC = "F20" ; + +#NET "SYSEN" LOC = "C11" ; + +## I2C +NET "db_scl" LOC = "F19" ; +NET "db_sda" LOC = "F18" ; + +## SPI +### DBoard SPI +NET "db_sclk_rx" LOC = "D21" ; +NET "db_miso_rx" LOC = "D22" ; +NET "db_mosi_rx" LOC = "D20" ; +NET "db_sen_rx" LOC = "E19" ; +NET "db_sclk_tx" LOC = "F21" ; +NET "db_miso_tx" LOC = "E20" ; +NET "db_mosi_tx" LOC = "G17" ; +NET "db_sen_tx" LOC = "G18" ; + +### AD9862 SPI and aux SPI Interfaces +#NET "aux_sdi_codec" LOC = "G3" ; +#NET "aux_sdo_codec" LOC = "F3" ; +#NET "aux_sclk_codec" LOC = "C1" ; +NET "sen_codec" LOC = "F5" |IOSTANDARD = LVCMOS33; +NET "mosi_codec" LOC = "F4" |IOSTANDARD = LVCMOS33; +NET "miso_codec" LOC = "H4" ; +NET "sclk_codec" LOC = "H3" |IOSTANDARD = LVCMOS33; + +### Clock Gen SPI +NET "cgen_miso" LOC = "F22" ; +NET "cgen_mosi" LOC = "E22" ; +NET "cgen_sclk" LOC = "J19" ; +NET "cgen_sen_b" LOC = "H20" ; + +## Clock gen control +NET "cgen_st_status" LOC = "P20" ; +NET "cgen_st_ld" LOC = "R17" ; +NET "cgen_st_refmon" LOC = "P17" ; +NET "cgen_sync_b" LOC = "U18" ; +NET "cgen_ref_sel" LOC = "U19" ; + +## Debug pins +NET "debug_led<3>" LOC = "Y15" ; +NET "debug_led<2>" LOC = "K16" ; +NET "debug_led<1>" LOC = "J17" ; +NET "debug_led<0>" LOC = "H22" ; +NET "debug<0>" LOC = "G22" ; +NET "debug<1>" LOC = "H17" ; +NET "debug<2>" LOC = "H18" ; +NET "debug<3>" LOC = "K20" ; +NET "debug<4>" LOC = "J20" ; +NET "debug<5>" LOC = "K19" ; +NET "debug<6>" LOC = "K18" ; +NET "debug<7>" LOC = "L22" ; +NET "debug<8>" LOC = "K22" ; +NET "debug<9>" LOC = "N22" ; +NET "debug<10>" LOC = "M22" ; +NET "debug<11>" LOC = "N20" ; +NET "debug<12>" LOC = "N19" ; +NET "debug<13>" LOC = "R22" ; +NET "debug<14>" LOC = "P22" ; +NET "debug<15>" LOC = "N17" ; +NET "debug<16>" LOC = "P16" ; +NET "debug<17>" LOC = "U22" ; +NET "debug<18>" LOC = "P19" ; +NET "debug<19>" LOC = "R18" ; +NET "debug<20>" LOC = "U20" ; +NET "debug<21>" LOC = "T20" ; +NET "debug<22>" LOC = "R19" ; +NET "debug<23>" LOC = "R20" ; +NET "debug<24>" LOC = "W22" ; +NET "debug<25>" LOC = "Y22" ; +NET "debug<26>" LOC = "T18" ; +NET "debug<27>" LOC = "T17" ; +NET "debug<28>" LOC = "W19" ; +NET "debug<29>" LOC = "V20" ; +NET "debug<30>" LOC = "Y21" ; +NET "debug<31>" LOC = "AA22" ; +NET "debug_clk<0>" LOC = "N18" ; +NET "debug_clk<1>" LOC = "M17" ; + +NET "debug_pb" LOC = "C22" ; + +#NET "reset_codec" LOC = "C2" ; + +NET "RXSYNC" LOC = "F2" ; +NET "DB<11>" LOC = "G6" ; +NET "DB<10>" LOC = "G5" ; +NET "DB<9>" LOC = "E4" ; +NET "DB<8>" LOC = "E3" ; +NET "DB<7>" LOC = "H6" ; +NET "DB<6>" LOC = "H5" ; +NET "DB<5>" LOC = "H1" ; +NET "DB<4>" LOC = "G1" ; +NET "DB<3>" LOC = "K5" ; +NET "DB<2>" LOC = "K4" ; +NET "DB<1>" LOC = "H2" ; +NET "DB<0>" LOC = "L5" ; + +NET "DA<11>" LOC = "K6" ; +NET "DA<10>" LOC = "K3" ; +NET "DA<9>" LOC = "K2" ; +NET "DA<8>" LOC = "N1" ; +NET "DA<7>" LOC = "N5" ; +NET "DA<6>" LOC = "N6" ; +NET "DA<5>" LOC = "P2" ; +NET "DA<4>" LOC = "P1" ; +NET "DA<3>" LOC = "R6" ; +NET "DA<2>" LOC = "P6" ; +NET "DA<1>" LOC = "R1" ; +NET "DA<0>" LOC = "R2" ; + +NET "TX<13>" LOC = "T6" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<12>" LOC = "U1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<11>" LOC = "T1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<10>" LOC = "R5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<9>" LOC = "V1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<8>" LOC = "U2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<7>" LOC = "T4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<6>" LOC = "R3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<5>" LOC = "W1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<4>" LOC = "Y1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<3>" LOC = "V3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<2>" LOC = "V4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<1>" LOC = "W2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<0>" LOC = "W3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TXSYNC" LOC = "U5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TXBLANK" LOC = "U4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; + +NET "PPS_IN" LOC = "M5" ; + +NET "io_tx<0>" LOC = "AB20" ; +NET "io_tx<1>" LOC = "Y17" ; +NET "io_tx<2>" LOC = "Y16" ; +NET "io_tx<3>" LOC = "U16" ; +NET "io_tx<4>" LOC = "V16" ; +NET "io_tx<5>" LOC = "AB19" ; +NET "io_tx<6>" LOC = "AA19" ; +NET "io_tx<7>" LOC = "U14" ; +NET "io_tx<8>" LOC = "U15" ; +NET "io_tx<9>" LOC = "AB17" ; +NET "io_tx<10>" LOC = "AB18" ; +NET "io_tx<11>" LOC = "Y13" ; +NET "io_tx<12>" LOC = "W14" ; +NET "io_tx<13>" LOC = "U13" ; +NET "io_tx<14>" LOC = "AA15" ; +NET "io_tx<15>" LOC = "AB14" ; + +NET "io_rx<0>" LOC = "Y8" ; +NET "io_rx<1>" LOC = "Y9" ; +NET "io_rx<2>" LOC = "V7" ; +NET "io_rx<3>" LOC = "U8" ; +NET "io_rx<4>" LOC = "V10" ; +NET "io_rx<5>" LOC = "U9" ; +NET "io_rx<6>" LOC = "AB7" ; +NET "io_rx<7>" LOC = "AA8" ; +NET "io_rx<8>" LOC = "W8" ; +NET "io_rx<9>" LOC = "V8" ; +NET "io_rx<10>" LOC = "AB5" ; +NET "io_rx<11>" LOC = "AB6" ; +NET "io_rx<12>" LOC = "AB4" ; +NET "io_rx<13>" LOC = "AA4" ; +NET "io_rx<14>" LOC = "W5" ; +NET "io_rx<15>" LOC = "Y4" ; + +#NET "CLKOUT2_CODEC" LOC = "U12" ; +#NET "CLKOUT1_CODEC" LOC = "V12" ; + +## FPGA Config Pins +#NET "fpga_cfg_prog_b" LOC = "A2" ; +#NET "fpga_cfg_done" LOC = "AB21" ; +#NET "fpga_cfg_din" LOC = "W17" ; +#NET "fpga_cfg_cclk" LOC = "V17" ; +#NET "fpga_cfg_init_b" LOC = "W15" ; + +## Unused +#NET "unnamed_net53" LOC = "B1" ; # TMS +#NET "unnamed_net52" LOC = "B22" ; # TDO +#NET "unnamed_net51" LOC = "D2" ; # TDI +#NET "unnamed_net50" LOC = "A21" ; # TCK +#NET "unnamed_net59" LOC = "F7" ; # PUDC_B +#NET "unnamed_net58" LOC = "V6" ; # M2 +#NET "unnamed_net57" LOC = "AA3" ; # M1 +#NET "unnamed_net56" LOC = "AB3" ; # M0 +#NET "GND" LOC = "V19" ; # Suspend, unused diff --git a/fpga/usrp2/top/E1x0/E1x0.v b/fpga/usrp2/top/E1x0/E1x0.v new file mode 100644 index 000000000..e7b0a4e00 --- /dev/null +++ b/fpga/usrp2/top/E1x0/E1x0.v @@ -0,0 +1,196 @@ +// +// Copyright 2011-2012 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module E1x0 + (input CLK_FPGA_P, input CLK_FPGA_N, // Diff + output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + input debug_pb, output FPGA_TXD, input FPGA_RXD, + output fpga_txd1, input fpga_rxd1, input overo_txd1, output overo_rxd1, + + // GPMC + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, + input EM_NWE, input EM_NOE, + + inout db_sda, inout db_scl, // I2C + + output db_sclk_tx, output db_sen_tx, output db_mosi_tx, input db_miso_tx, // DB TX SPI + output db_sclk_rx, output db_sen_rx, output db_mosi_rx, input db_miso_rx, // DB TX SPI + output sclk_codec, output sen_codec, output mosi_codec, input miso_codec, // AD9862 main SPI + output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso, // Clock gen SPI + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, + input overo_gpio65, input overo_gpio128, input overo_gpio145, output overo_gpio147, //aux SPI + + output overo_gpio144, output overo_gpio146, // Fifo controls + input overo_gpio0, input overo_gpio14, input overo_gpio21, input overo_gpio22, // Misc GPIO + input overo_gpio23, input overo_gpio64, input overo_gpio127, // Misc GPIO + input overo_gpio176, input overo_gpio163, input overo_gpio170, // Misc GPIO + + inout [15:0] io_tx, inout [15:0] io_rx, + + output [13:0] TX, output TXSYNC, output TXBLANK, + input [11:0] DA, input [11:0] DB, input RXSYNC, + + input PPS_IN + ); + + assign FPGA_TXD = 0; //dont care + + // ///////////////////////////////////////////////////////////////////////// + // Clocking + wire clk_fpga; + wire reset; + + reg async_reset; + always @(negedge EM_CLK) begin + async_reset <= ~EM_NCS6 && ~EM_NWE && (EM_A[9:2] == 8'hff) && EM_D[0]; + end + + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) + clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + + reset_sync reset_sync(.clk(clk_fpga), .reset_in(async_reset), .reset_out(reset)); + + // ///////////////////////////////////////////////////////////////////////// + // UART level conversion + assign fpga_txd1 = overo_txd1; + assign overo_rxd1 = fpga_rxd1; + + // SPI + wire mosi, sclk, miso; + assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0; + assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0; + assign { sclk_codec, mosi_codec } = ~sen_codec ? {sclk,mosi} : 2'b0; + //assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0; //replaced by aux spi + assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) | + (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso); + + //assign the aux spi to the cgen (bypasses control fifo) + assign cgen_sclk = overo_gpio65; + assign cgen_sen_b = overo_gpio128; + assign cgen_mosi = overo_gpio145; + wire has_resp; //re-purpose gpio for interrupt when we are not using aux spi + assign overo_gpio147 = (cgen_sen_b == 1'b0)? cgen_miso : has_resp; + + wire _cgen_sen_b; + //assign cgen_sen_b = _cgen_sen_b; //replaced by aux spi + + // ///////////////////////////////////////////////////////////////////////// + // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL + + assign TXBLANK = 0; + wire [13:0] tx_i, tx_q; + + reg[13:0] delay_q; + always @(posedge clk_fpga) + delay_q <= tx_q; + + genvar i; + generate + for(i=0;i<14;i=i+1) + begin : gen_dacout + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_inst (.Q(TX[i]), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(tx_i[i]), // 1-bit data input (associated with C0) + .D1(delay_q[i]), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + end // block: gen_dacout + endgenerate + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(1'b0), // 1-bit data input (associated with C0) + .D1(1'b1), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + + // ///////////////////////////////////////////////////////////////////////// + // Main Core + wire [35:0] rx_data, tx_data, ctrl_data, resp_data; + wire rx_src_rdy, rx_dst_rdy, tx_src_rdy, tx_dst_rdy, resp_src_rdy, resp_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy; + wire dsp_rx_run, dsp_tx_run; + wire [7:0] sen8; + assign {_cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx} = sen8[3:0]; + wire [31:0] core_debug; + + assign debug_led = ~{PPS_IN, dsp_tx_run, dsp_rx_run, cgen_st_ld}; + wire cgen_sync; + assign { cgen_sync_b, cgen_ref_sel } = {~cgen_sync, 1'b1}; + + u1plus_core #( + .NUM_RX_DSPS(2), + .DSP_RX_XTRA_FIFOSIZE(10), + .DSP_TX_XTRA_FIFOSIZE(10), + .USE_PACKET_PADDER(0) + ) core( + .clk(clk_fpga), .reset(reset), + .debug(core_debug), .debug_clk(debug_clk), + + .rx_data(rx_data), .rx_src_rdy(rx_src_rdy), .rx_dst_rdy(rx_dst_rdy), + .tx_data(tx_data), .tx_src_rdy(tx_src_rdy), .tx_dst_rdy(tx_dst_rdy), + .ctrl_data(ctrl_data), .ctrl_src_rdy(ctrl_src_rdy), .ctrl_dst_rdy(ctrl_dst_rdy), + .resp_data(resp_data), .resp_src_rdy(resp_src_rdy), .resp_dst_rdy(resp_dst_rdy), + + .dsp_rx_run(dsp_rx_run), .dsp_tx_run(dsp_tx_run), + .clock_sync(cgen_sync), + + .db_sda(db_sda), .db_scl(db_scl), + .sclk(sclk), .sen(sen8), .mosi(mosi), .miso(miso), + .io_tx(io_tx), .io_rx(io_rx), + .tx_i(tx_i), .tx_q(tx_q), + .rx_i(DA), .rx_q(DB), + .pps_in(PPS_IN) ); + + // ///////////////////////////////////////////////////////////////////////// + // Interface between GPMC/host + wire [31:0] gpmc_debug; + + gpmc #(.TXFIFOSIZE(13), .RXFIFOSIZE(13)) + gpmc (.arst(async_reset), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), + .EM_NOE(EM_NOE), + + .rx_have_data(overo_gpio146), .tx_have_space(overo_gpio144), + .resp_have_data(has_resp), + + .fifo_clk(clk_fpga), .fifo_rst(reset), + .rx_data(rx_data), .rx_src_rdy(rx_src_rdy), .rx_dst_rdy(rx_dst_rdy), + .tx_data(tx_data), .tx_src_rdy(tx_src_rdy), .tx_dst_rdy(tx_dst_rdy), + .ctrl_data(ctrl_data), .ctrl_src_rdy(ctrl_src_rdy), .ctrl_dst_rdy(ctrl_dst_rdy), + .resp_data(resp_data), .resp_src_rdy(resp_src_rdy), .resp_dst_rdy(resp_dst_rdy), + + .debug(gpmc_debug)); + + //assign debug = gpmc_debug; + assign debug = core_debug; + +endmodule // E1x0 diff --git a/fpga/usrp2/top/E1x0/Makefile b/fpga/usrp2/top/E1x0/Makefile new file mode 100644 index 000000000..0ca8ed2dd --- /dev/null +++ b/fpga/usrp2/top/E1x0/Makefile @@ -0,0 +1,17 @@ +# +# Copyright 2011 Ettus Research LLC +# + +all: E100 E110 + find -name "*.twr" | xargs grep constraint | grep met + +clean: + rm -rf build* + +E100: + make -f Makefile.$@ bin + +E110: + make -f Makefile.$@ bin + +.PHONY: all clean diff --git a/fpga/usrp2/top/E1x0/Makefile.E100 b/fpga/usrp2/top/E1x0/Makefile.E100 new file mode 100644 index 000000000..92334d987 --- /dev/null +++ b/fpga/usrp2/top/E1x0/Makefile.E100 @@ -0,0 +1,106 @@ +# +# Copyright 2008-2012 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = E1x0 +BUILD_DIR = $(abspath build$(ISE)-E100) + +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../gpmc/Makefile.srcs + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +../B100/u1plus_core.v \ +E1x0.v \ +E1x0.ucf \ +timing.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ +$(GPMC_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto \ +"Verilog Macros" "$(CUSTOM_DEFS)" + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Generate Detailed MAP Report" TRUE \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/E1x0/Makefile.E110 b/fpga/usrp2/top/E1x0/Makefile.E110 new file mode 100644 index 000000000..e5be8d2fa --- /dev/null +++ b/fpga/usrp2/top/E1x0/Makefile.E110 @@ -0,0 +1,106 @@ +# +# Copyright 2008-2012 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = E1x0 +BUILD_DIR = $(abspath build$(ISE)-E110) + +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../gpmc/Makefile.srcs + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd3400a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +../B100/u1plus_core.v \ +E1x0.v \ +E1x0.ucf \ +timing.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ +$(GPMC_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto \ +"Verilog Macros" "$(CUSTOM_DEFS)" + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Generate Detailed MAP Report" TRUE \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/E1x0/README b/fpga/usrp2/top/E1x0/README new file mode 100644 index 000000000..14c7a4955 --- /dev/null +++ b/fpga/usrp2/top/E1x0/README @@ -0,0 +1,4 @@ + +make clean +make sim +./tb_u1e -lxt2 diff --git a/fpga/usrp2/top/E1x0/cmdfile b/fpga/usrp2/top/E1x0/cmdfile new file mode 100644 index 000000000..291c723b8 --- /dev/null +++ b/fpga/usrp2/top/E1x0/cmdfile @@ -0,0 +1,20 @@ + +# My stuff +-y . +-y ../../control_lib +-y ../../control_lib/newfifo +-y ../../sdr_lib +-y ../../timing +-y ../../coregen +-y ../../gpmc + +# Models +-y ../../models +-y /opt/Xilinx/10.1/ISE/verilog/src/unisims + +# Open Cores +-y ../../opencores/spi/rtl/verilog ++incdir+../../opencores/spi/rtl/verilog +-y ../../opencores/i2c/rtl/verilog ++incdir+../../opencores/i2c/rtl/verilog + diff --git a/fpga/usrp2/top/E1x0/core_compile b/fpga/usrp2/top/E1x0/core_compile new file mode 100755 index 000000000..ab992f29d --- /dev/null +++ b/fpga/usrp2/top/E1x0/core_compile @@ -0,0 +1,3 @@ +iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../B100 -y $XILINX/verilog/src/unisims E1x0.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models + + diff --git a/fpga/usrp2/top/E1x0/make.sim b/fpga/usrp2/top/E1x0/make.sim new file mode 100644 index 000000000..1c163884c --- /dev/null +++ b/fpga/usrp2/top/E1x0/make.sim @@ -0,0 +1,7 @@ +all: sim + +sim: + iverilog -Wimplicit -Wportbind -c cmdfile tb_u1e.v -o tb_u1e + +clean: + rm -f tb_u1e *.vcd *.lxt a.out diff --git a/fpga/usrp2/top/E1x0/tb_u1e.v b/fpga/usrp2/top/E1x0/tb_u1e.v new file mode 100644 index 000000000..188190f04 --- /dev/null +++ b/fpga/usrp2/top/E1x0/tb_u1e.v @@ -0,0 +1,58 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +`timescale 1ps / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module tb_u1e(); + + wire [2:0] debug_led; + wire [31:0] debug; + wire [1:0] debug_clk; + + xlnx_glbl glbl (.GSR(),.GTS()); + + initial begin + $dumpfile("tb_u1e.lxt"); + $dumpvars(0,tb_u1e); + end + + // GPMC + wire EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE; + wire [15:0] EM_D; + wire [10:1] EM_A; + wire [1:0] EM_NBE; + + reg clk_fpga = 0, rst_fpga = 1; + always #15625 clk_fpga = ~clk_fpga; + + initial #200000 + @(posedge clk_fpga) + rst_fpga <= 0; + + u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(rst_fpga), + .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); + + gpmc_model_async gpmc_model_async + (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); + +endmodule // tb_u1e diff --git a/fpga/usrp2/top/E1x0/timing.ucf b/fpga/usrp2/top/E1x0/timing.ucf new file mode 100644 index 000000000..7d3d9e090 --- /dev/null +++ b/fpga/usrp2/top/E1x0/timing.ucf @@ -0,0 +1,23 @@ + +NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; + +NET "EM_CLK" TNM_NET = "EM_CLK"; +TIMESPEC "TS_em_clk" = PERIOD "EM_CLK" 18867 ps HIGH 50 %; + +#constrain GPMC IO +INST "EM_D<*>" TNM = gpmc_net_out; +INST "EM_D<*>" TNM = gpmc_net; +INST "EM_A<*>" TNM = gpmc_net; +INST "EM_NCS4" TNM = gpmc_net; +INST "EM_NCS6" TNM = gpmc_net; +INST "EM_NWE" TNM = gpmc_net; +INST "EM_NOE" TNM = gpmc_net; + +TIMEGRP "gpmc_net" OFFSET = IN 6 ns VALID 12 ns BEFORE "EM_CLK" FALLING; +TIMEGRP "gpmc_net_out" OFFSET = OUT 14 ns AFTER "EM_CLK" RISING; //2 clock cyc per read + +#constrain interrupt lines +NET "overo_gpio144" MAXDELAY = 5.5 ns; #have space +NET "overo_gpio146" MAXDELAY = 5.5 ns; #have data +NET "overo_gpio147" MAXDELAY = 5.5 ns; #have msg/aux spi miso diff --git a/fpga/usrp2/top/Makefile.common b/fpga/usrp2/top/Makefile.common new file mode 100644 index 000000000..3b71e7b13 --- /dev/null +++ b/fpga/usrp2/top/Makefile.common @@ -0,0 +1,64 @@ +# +# Copyright 2008-2011 Ettus Research LLC +# + +################################################## +# Constants +################################################## +ISE_VER = $(shell xtclsh -h | head -n1 | cut -f2 -d" " | cut -f1 -d.) +ifeq ($(ISE_VER),10) + ISE_EXT = ise +else + ISE_EXT = xise +endif +BASE_DIR = $(abspath ..) +ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl +SANITY_CHECKER = python $(BASE_DIR)/python/check_inout.py +TIMING_CHECKER = python $(BASE_DIR)/python/check_timing.py +ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).$(ISE_EXT) +BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bin +BIT_FILE = $(BUILD_DIR)/$(TOP_MODULE).bit +MCS_FILE = $(BUILD_DIR)/$(TOP_MODULE).mcs +TWR_FILE = $(BUILD_DIR)/$(TOP_MODULE).twr + +################################################## +# Global Targets +################################################## +all: bin + +proj: $(ISE_FILE) + +check: $(ISE_FILE) + $(SANITY_CHECKER) $(TOP_MODULE).v $(TOP_MODULE).ucf + $(ISE_HELPER) "Check Syntax" + +synth: $(ISE_FILE) + $(ISE_HELPER) "Synthesize - XST" + +bin: check $(BIN_FILE) + $(TIMING_CHECKER) $(TWR_FILE) + +mcs: $(MCS_FILE) + +clean: + $(RM) -r $(BUILD_DIR) + +.PHONY: all proj check synth bin mcs clean + +################################################## +# Dependency Targets +################################################## +.SECONDEXPANSION: +$(ISE_FILE): $$(SOURCES) $$(MAKEFILE_LIST) + @echo $@ + $(ISE_HELPER) "" + +$(BIN_FILE): $(ISE_FILE) $$(SOURCES) $$(MAKEFILE_LIST) + @echo $@ + $(ISE_HELPER) "Generate Programming File" + touch $@ + +$(MCS_FILE): $(BIN_FILE) + promgen -w -spi -p mcs -o $(MCS_FILE) -s 4096 -u 0 $(BIT_FILE) + +.EXPORT_ALL_VARIABLES: diff --git a/fpga/usrp2/top/N2x0/.gitignore b/fpga/usrp2/top/N2x0/.gitignore new file mode 100644 index 000000000..1b2211df0 --- /dev/null +++ b/fpga/usrp2/top/N2x0/.gitignore @@ -0,0 +1 @@ +build* diff --git a/fpga/usrp2/top/N2x0/Makefile b/fpga/usrp2/top/N2x0/Makefile new file mode 100644 index 000000000..b6a3d9624 --- /dev/null +++ b/fpga/usrp2/top/N2x0/Makefile @@ -0,0 +1,23 @@ +# +# Copyright 2011 Ettus Research LLC +# + +all: N200R3 N210R3 N200R4 N210R4 + find -name "*.twr" | xargs grep constraint | grep met + +clean: + rm -rf build* + +N200R3: + make -f Makefile.$@ bin + +N210R3: + make -f Makefile.$@ bin + +N200R4: + make -f Makefile.$@ bin + +N210R4: + make -f Makefile.$@ bin + +.PHONY: all clean diff --git a/fpga/usrp2/top/N2x0/Makefile.N200R3 b/fpga/usrp2/top/N2x0/Makefile.N200R3 new file mode 100644 index 000000000..07b955d13 --- /dev/null +++ b/fpga/usrp2/top/N2x0/Makefile.N200R3 @@ -0,0 +1,104 @@ +# +# Copyright 2008-2012 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u2plus +BUILD_DIR = $(abspath build$(ISE)-N200R3) + +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extramfifo/Makefile.srcs + + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u2plus_core.v \ +u2plus.v \ +u2plus.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto \ +"Verilog Macros" "$(CUSTOM_DEFS)" + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Generate Detailed MAP Report" TRUE \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/N2x0/Makefile.N200R4 b/fpga/usrp2/top/N2x0/Makefile.N200R4 new file mode 100644 index 000000000..8b1090308 --- /dev/null +++ b/fpga/usrp2/top/N2x0/Makefile.N200R4 @@ -0,0 +1,105 @@ +# +# Copyright 2008-2012 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u2plus +BUILD_DIR = $(abspath build$(ISE)-N200R4) + +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extramfifo/Makefile.srcs + + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +capture_ddrlvds.v \ +u2plus_core.v \ +u2plus.v \ +u2plus.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto \ +"Verilog Macros" "LVDS=1 $(CUSTOM_DEFS)" + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Generate Detailed MAP Report" TRUE \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/N2x0/Makefile.N210R3 b/fpga/usrp2/top/N2x0/Makefile.N210R3 new file mode 100644 index 000000000..411aa20f1 --- /dev/null +++ b/fpga/usrp2/top/N2x0/Makefile.N210R3 @@ -0,0 +1,104 @@ +# +# Copyright 2008-2012 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u2plus +BUILD_DIR = $(abspath build$(ISE)-N210R3) + +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extramfifo/Makefile.srcs + + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd3400a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u2plus_core.v \ +u2plus.v \ +u2plus.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto \ +"Verilog Macros" "$(CUSTOM_DEFS)" + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Generate Detailed MAP Report" TRUE \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/N2x0/Makefile.N210R4 b/fpga/usrp2/top/N2x0/Makefile.N210R4 new file mode 100644 index 000000000..44ce17b3f --- /dev/null +++ b/fpga/usrp2/top/N2x0/Makefile.N210R4 @@ -0,0 +1,105 @@ +# +# Copyright 2008-2012 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u2plus +BUILD_DIR = $(abspath build$(ISE)-N210R4) + +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extramfifo/Makefile.srcs + + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd3400a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +capture_ddrlvds.v \ +u2plus_core.v \ +u2plus.v \ +u2plus.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto \ +"Verilog Macros" "LVDS=1 $(CUSTOM_DEFS)" + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Generate Detailed MAP Report" TRUE \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/N2x0/bootloader.rmi b/fpga/usrp2/top/N2x0/bootloader.rmi new file mode 100644 index 000000000..cf51f52b4 --- /dev/null +++ b/fpga/usrp2/top/N2x0/bootloader.rmi @@ -0,0 +1,512 @@ +defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_dbaa0400_3a0b0b80_80e7e80c_82700b0b_0b0b0b0b; +defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_80dbf42d_88080b0b_80088408; +defparam bootram.RAM0.INIT_02=256'h00000000_00000000_04000000_ffff0652_832b2a83_81058205_72830609_71fd0608; +defparam bootram.RAM0.INIT_03=256'h83a70400_0b0b0b0b_7383ffff_2b2b0906_05820583_83060981_83ffff73_71fd0608; +defparam bootram.RAM0.INIT_04=256'h00000000_00000000_53510400_070a8106_73097306_09060906_72057373_72098105; +defparam bootram.RAM0.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722473; +defparam bootram.RAM0.INIT_06=256'h00000000_53510400_81065151_0a31050a_0a720a10_30720a10_71068106_71737109; +defparam bootram.RAM0.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722673; +defparam bootram.RAM0.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_c4040000_0b0b0b88; +defparam bootram.RAM0.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_0a535104_720a722b; +defparam bootram.RAM0.INIT_0B=256'h00000000_00000000_00000000_00000000_05040000_0b0b88a7_0981050b_72729f06; +defparam bootram.RAM0.INIT_0C=256'h00000000_00000000_04000000_06075351_8106ff05_0974090a_739f062a_72722aff; +defparam bootram.RAM0.INIT_0D=256'h00000000_0c515104_0772fc06_832b0b2b_81058205_73830609_020d0406_71715351; +defparam bootram.RAM0.INIT_0E=256'h00000000_00000000_00000000_51040000_0a810653_81050906_72050970_72098105; +defparam bootram.RAM0.INIT_0F=256'h00000000_00000000_00000000_53510400_0a098106_81050906_72050970_72098105; +defparam bootram.RAM0.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_52040000_71098105; +defparam bootram.RAM0.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_04000000_05055351_72720981; +defparam bootram.RAM0.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_07535104_73730906_72097206; +defparam bootram.RAM0.INIT_13=256'h00000000_00000000_04000000_81ff0652_1010102a_81058305_72830609_71fc0608; +defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88aa0400_060b0b0b_10100508_d4738306_0b0b80e7_71fc0608; +defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_cb2d5050_0b0b80d2_88087575_80088408; +defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_fd2d5050_0b0b80d3_88087575_80088408; +defparam bootram.RAM0.INIT_17=256'h04000000_07515151_05ff0506_73097274_70547106_8106ff05_0509060a_72097081; +defparam bootram.RAM0.INIT_18=256'h51040000_06075151_7405ff05_06730972_05705471_098106ff_0509060a_72097081; +defparam bootram.RAM0.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_05ff0504; +defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_80e7e40c_810b0b0b; +defparam bootram.RAM0.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_04000000_71810552; +defparam bootram.RAM0.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_04000000_10100552_02840572; +defparam bootram.RAM0.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_020d0400_05715351_717105ff; +defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_d3f13f04_82813f80; +defparam bootram.RAM0.INIT_21=256'hfc060c51_102b0772_83051010_06098105_ff067383_51047381_10101053_10101010; +defparam bootram.RAM0.INIT_22=256'h51535104_72ed3851_0a100a53_71105272_09720605_8106ff05_72728072_51043c04; +defparam bootram.RAM0.INIT_23=256'h800b80e8_b40c82a0_0b0b80e8_8380800b_822ebd38_80e7e808_802ea438_80e7e408; +defparam bootram.RAM0.INIT_24=256'h0b80e8b8_80808280_e8b40cf8_0b0b0b80_808080a4_bc0c04f8_800b80e8_b80c8290; +defparam bootram.RAM0.INIT_25=256'h940b80e8_80c0a880_80e8b40c_8c0b0b0b_80c0a880_e8bc0c04_84800b80_0cf88080; +defparam bootram.RAM0.INIT_26=256'h70085252_80e7f008_5170a738_80e8c033_04ff3d0d_80e8bc0c_80dca40b_b80c0b0b; +defparam bootram.RAM0.INIT_27=256'hc034833d_810b80e8_5270ee38_08700852_2d80e7f0_e7f00c70_38841280_70802e94; +defparam bootram.RAM0.INIT_28=256'h38823d0d_09810685_800b802e_0b0b0b0b_802e8e38_80e8b008_3d0d0b0b_0d040480; +defparam bootram.RAM0.INIT_29=256'h389d3d22_5b7a80c4_0da13d08_0404e63d_3f823d0d_0b0bf5d4_e8b0510b_040b0b80; +defparam bootram.RAM0.INIT_2A=256'h862e8c38_39798380_8e3882fb_8380842e_248b3879_79838085_852eac38_5a798380; +defparam bootram.RAM0.INIT_2B=256'h0c82d439_7a80e8c4_81e4d00c_0c86397a_0b81e2cc_0c8e3981_0b81e18c_82f13981; +defparam bootram.RAM0.INIT_2C=256'h82b53979_842e9f38_38798380_8085248b_a7387983_8380852e_225b4079_800ba03d; +defparam bootram.RAM0.INIT_2D=256'h4288539d_83409a3d_81408339_82408739_3882a439_80872e8c_8b387983_8380862e; +defparam bootram.RAM0.INIT_2E=256'h9d3df405_963d7053_80cbe43f_3d526251_4388539d_f23f983d_615180cb_3d880552; +defparam bootram.RAM0.INIT_2F=256'h3f800808_68458cde_22993d23_08498e1b_fb38881b_3d082780_3f8f0ba3_5241acb8; +defparam bootram.RAM0.INIT_30=256'h9c3de405_08456052_cf3f8008_2e88388c_5b5b7a7a_06657b06_8008087a_5a8ccd3f; +defparam bootram.RAM0.INIT_31=256'hff5b7a44_51a0da3f_9c3de405_81068b38_797b2e09_065a805b_800881ff_51abf93f; +defparam bootram.RAM0.INIT_32=256'h887c26ed_34811c5c_5b79337b_3d7d055b_5c7b1d9e_0b833d5e_e0055480_84559c3d; +defparam bootram.RAM0.INIT_33=256'h621d5b5b_5e5c7b1d_800b883d_615b5f5f_08028405_8bdc3f80_519ff53f_389f3d22; +defparam bootram.RAM0.INIT_34=256'h811c5c88_79337b34_631d5b5b_5e5c7b1d_800b901f_7c26ef38_811c5c88_79337b34; +defparam bootram.RAM0.INIT_35=256'h805c7b1e_7c26ef38_811c5c86_79337b34_7f1d5b5b_5e5c7b1d_800b881f_7c26ef38; +defparam bootram.RAM0.INIT_36=256'h84120859_3d0d686a_3d0d04ee_9af13f9c_7c26ef38_811c5c86_79337b34_611d5b5b; +defparam bootram.RAM0.INIT_37=256'h95e93f80_80dca851_75538c52_802e8c38_2e943875_0856758c_279c3877_5a588379; +defparam bootram.RAM0.INIT_38=256'hff9f1756_8818085d_8c5ba05c_d63fa057_dcf85195_53a45280_268e3878_e15778a3; +defparam bootram.RAM0.INIT_39=256'heb399518_08085e81_8a9a3f80_0480c15c_05567508_2980dee8_81387584_75922682; +defparam bootram.RAM0.INIT_3A=256'h97193357_0852800b_08538c18_33549018_76559618_83388457_7580f22e_33568257; +defparam bootram.RAM0.INIT_3B=256'h3dea0553_33705495_b3398d18_80d35c81_3f80085f_76519791_83388157_5775772e; +defparam bootram.RAM0.INIT_3C=256'h3f80c85c_52568ecc_538c1933_70548e19_398d1833_80c95c94_568dbf3f_8c193352; +defparam bootram.RAM0.INIT_3D=256'h058c1908_2980dfb4_c2387584_75852680_33ff0556_ff399418_b5053480_75028405; +defparam bootram.RAM0.INIT_3E=256'h39768429_2277239b_a2399218_1808770c_5fa93990_ae397622_0476085f_58567508; +defparam bootram.RAM0.INIT_3F=256'h785e80cc_d25cad39_710c5680_05901908_2980e8c4_8e397684_70084056_80e8c405; +defparam bootram.RAM1.INIT_00=256'h81185888_75337734_79055757_7719963d_833d5a58_0554800b_55943ddc_5c8c1808; +defparam bootram.RAM1.INIT_01=256'h57753377_3d790557_58771996_0b833d5a_dc055480_a455943d_a439a05c_7826ed38; +defparam bootram.RAM1.INIT_02=256'hc4525393_705380dd_fe3d0d74_943d0d04_519c8d3f_38838080_887826ed_34811858; +defparam bootram.RAM1.INIT_03=256'h88b33f72_a0527251_a33f8d39_90b83f9d_c43f8151_52a05188_2e9238a0_863f7280; +defparam bootram.RAM1.INIT_04=256'h805192c7_8a5280de_5189a43f_3f80dde4_973fa5de_fa3d0d82_843d0d04_5190a73f; +defparam bootram.RAM1.INIT_05=256'h90fc3f88_3f800851_e23f878e_abe53f87_80e8e00c_be3f820b_dea05192_3f8c5280; +defparam bootram.RAM1.INIT_06=256'h95b83f86_52800851_86f03f73_3f800854_b53f8780_91963f88_3f800851_c13f878c; +defparam bootram.RAM1.INIT_07=256'h83808451_3f8ab252_805195fe_d7528380_95c23f8d_518f873f_85528008_ef3f8380; +defparam bootram.RAM1.INIT_08=256'h875195d6_b2528380_95e03f8a_83808551_3f8ab252_865195ea_b2528380_95f43f8a; +defparam bootram.RAM1.INIT_09=256'h8e3faea0_90d451ac_518ef33f_a7bb3f80_83809251_5195cb3f_52838082_3f80c3cf; +defparam bootram.RAM1.INIT_0A=256'h82fdee2e_22555573_80088e05_80c93876_8008802e_3f800856_05518eea_3f883dfc; +defparam bootram.RAM1.INIT_0B=256'h90e93f94_80decc51_80089a38_80c6f03f_08900551_dec45280_38845380_098106ad; +defparam bootram.RAM1.INIT_0C=256'h8e3f8ce1_8def3fa7_519c863f_39745275_85e03f88_f93f7351_8fda3f86_16705254; +defparam bootram.RAM1.INIT_0D=256'h51868f3f_3f9f5280_963f88e6_87ea3f8c_3f82b73f_c23f92b1_fe3d0d86_3fff9e39; +defparam bootram.RAM1.INIT_0E=256'h885185d1_c83f8852_82ac518b_5185de3f_3f845284_ac518bd5_85eb3f82_9f528051; +defparam bootram.RAM1.INIT_0F=256'h3f80e451_805185b5_82539f52_518bae3f_c43f82ac_52905185_8bbb3f90_3f82ac51; +defparam bootram.RAM1.INIT_10=256'h85b03f9f_9f529e51_8025df38_ff135372_518b923f_a83f80e4_529c5185_8b9f3f9f; +defparam bootram.RAM1.INIT_11=256'h8b2a8106_808c0870_803d0d82_843d0d04_810b800c_81e0840c_8c3f890b_52815185; +defparam bootram.RAM1.INIT_12=256'h57585957_82055a57_30708025_a7053370_7f028c05_3d0d7a7d_3d0d04f9_800c5182; +defparam bootram.RAM1.INIT_13=256'h51538054_30709f2a_388a5573_88557383_832e8838_88055575_38728025_75822e93; +defparam bootram.RAM1.INIT_14=256'h54548054_842b0751_fe057072_05777131_76812cff_802e9738_38725472_8177259e; +defparam bootram.RAM1.INIT_15=256'h51b0b43f_73528118_51b0bc3f_ff065277_c63f7281_527b51b0_81805474_86397353; +defparam bootram.RAM1.INIT_16=256'h527551fe_54bd5378_815580ca_9f053356_fb3d0d02_893d0d04_51b0ac3f_815280da; +defparam bootram.RAM1.INIT_17=256'h81ff0653_bb3f8008_51d63ffe_3f815281_c551b083_0d815280_0d04fe3d_e63f873d; +defparam bootram.RAM1.INIT_18=256'h81705654_787a5757_04fa3d0d_53843d0d_81e0800c_08709007_3881e080_72802ef3; +defparam bootram.RAM1.INIT_19=256'h38805581_81ff2e83_71335271_83388054_5270802e_17703352_279e3872_80537276; +defparam bootram.RAM1.INIT_1A=256'h33557481_0d80e8e4_0d04fc3d_800c883d_38815170_70802e83_74740751_1353df39; +defparam bootram.RAM1.INIT_1B=256'h74802e95_81ff0655_9e3f8008_80d051b0_e8538252_865480e8_80e8e434_e138810b; +defparam bootram.RAM1.INIT_1C=256'he8e85180_dfcc5280_38865380_74802e8f_81ff0655_8c3f8008_e8e851ff_38865280; +defparam bootram.RAM1.INIT_1D=256'h845280e8_802e9538_ff065574_3f800881_d051afe3_538c5280_5480e8f0_c0993f84; +defparam bootram.RAM1.INIT_1E=256'hf453b852_845480e8_80e8f00c_80dfd408_802e8938_ff065574_3f800881_f051fed1; +defparam bootram.RAM1.INIT_1F=256'h81ff0655_9c3f8008_e8f451fe_38845280_74802e95_81ff0655_ae3f8008_80d051af; +defparam bootram.RAM1.INIT_20=256'h0881ff06_aef93f80_5280d051_e8f85388_0c845480_0880e8f4_3880dfd8_74802e89; +defparam bootram.RAM1.INIT_21=256'hdc0880e8_893880df_5574802e_0881ff06_fde73f80_80e8f851_95388452_5574802e; +defparam bootram.RAM1.INIT_22=256'h3f80e8f8_0c04fdfa_e8f00b80_fe843f80_0b800c04_3f80e8e8_0d04fe8e_f80c863d; +defparam bootram.RAM1.INIT_23=256'had993f80_5280d051_5475538c_0d775684_0c04fb3d_e8f40b80_fdf03f80_0b800c04; +defparam bootram.RAM1.INIT_24=256'h80e8e434_3d0d810b_3d0d04fe_74800c87_80e8f00c_87387508_5574802e_0881ff06; +defparam bootram.RAM1.INIT_25=256'hfc080607_067180e8_73097375_04803d0d_3f843d0d_e851be8f_cc5280e8_945380df; +defparam bootram.RAM1.INIT_26=256'h077080e9_e9800806_75067180_0d730973_0d04803d_0c51823d_0c81e08c_7080e8fc; +defparam bootram.RAM1.INIT_27=256'h800c843d_81c73f72_53538051_3d0d7470_af3f04fe_3d0d0481_980c5182_800c81e0; +defparam bootram.RAM1.INIT_28=256'h06545472_337081ff_79565674_fb3d0d77_833d0d04_5181b63f_0d8a5280_0d04ff3d; +defparam bootram.RAM1.INIT_29=256'h3d0d7352_3d0d04ff_0b800c87_3fe53980_52558191_ff065376_81157481_802e9038; +defparam bootram.RAM1.INIT_2A=256'h0b800c84_80e73f80_8a527251_53ffbd3f_76537052_fe3d0d74_833d0d04_8051cd3f; +defparam bootram.RAM1.INIT_2B=256'h1234823d_3380e7f4_51028f05_803d0d72_833d0d04_8051dd3f_3d0d7352_3d0d04ff; +defparam bootram.RAM1.INIT_2C=256'hfe3d0d80_833d0d04_720c5351_e0057022_751080df_82908005_0d73a029_0d04ff3d; +defparam bootram.RAM1.INIT_2D=256'h38843d0d_827325e5_3f811353_527251ce_e7f81333_51c63f80_13335272_5380e7f4; +defparam bootram.RAM1.INIT_2E=256'h87388d52_2e098106_33537281_80e7f414_81069538_748a2e09_76785654_04fc3d0d; +defparam bootram.RAM1.INIT_2F=256'h04fe3d0d_0c863d0d_38748c15_72802ef8_84140853_90800554_73a02982_7351de3f; +defparam bootram.RAM1.INIT_30=256'h0d04ff3d_800c843d_12085372_2e853890_ff537080_11085252_90800588_74a02982; +defparam bootram.RAM1.INIT_31=256'h800b81a8_840c5181_882a81a8_a8800c70_81ff0681_e8802270_a8880c80_0d800b81; +defparam bootram.RAM1.INIT_32=256'h81a89008_2e818638_81517180_33555354_88059705_0d767802_0d04fd3d_880c833d; +defparam bootram.RAM1.INIT_33=256'ha8900870_a8900c81_81900b81_81a88c0c_72108107_5170f138_81065151_70862a70; +defparam bootram.RAM1.INIT_34=256'h70802eba_51515151_06708132_872a7081_a8900870_70f13881_06515151_812a7081; +defparam bootram.RAM1.INIT_35=256'h70810651_0870812a_0c81a890_7081a890_8338a051_5171812e_b13880e8_3871802e; +defparam bootram.RAM1.INIT_36=256'h0b81a890_883980c0_cc398151_34ff1252_70810556_08517074_3881a88c_515170f1; +defparam bootram.RAM1.INIT_37=256'h2a708106_90087086_535481a8_97053355_78028805_fd3d0d76_853d0d04_0c70800c; +defparam bootram.RAM1.INIT_38=256'h81a89008_81a8900c_81905170_802e8438_81d05171_81a88c0c_f1387210_51515170; +defparam bootram.RAM1.INIT_39=256'h5170802e_32515151_81067081_70872a70_81a89008_5170f138_81065151_70812a70; +defparam bootram.RAM1.INIT_3A=256'h900c81a8_517081a8_2e833890_d0517181_a88c0c80_38733381_802e80c5_80cf3871; +defparam bootram.RAM1.INIT_3B=256'h51515170_70813251_2a708106_90087087_f13881a8_51515170_2a708106_90087081; +defparam bootram.RAM1.INIT_3C=256'h0c853d0d_80517080_81a8900c_3980c00b_3981518a_5354ffb7_8114ff13_802e8e38; +defparam bootram.RAM1.INIT_3D=256'h8d9f7127_31515186_ac087073_085281b8_3881b8ac_7274259b_75548053_04fd3d0d; +defparam bootram.RAM1.INIT_3E=256'h0b828084_80800cef_81e20b82_8280880c_3d0dff0b_3d0d04ff_53e23985_f1388113; +defparam bootram.RAM1.INIT_3F=256'h38833d0d_708025f1_0cff1151_70840554_51a0f172_f3a85287_808c0c80_0cff0b82; +defparam bootram.RAM2.INIT_00=256'h74760652_f3a85555_53810b80_58515280_8c087106_70098280_82808808_04fb3d0d; +defparam bootram.RAM2.INIT_01=256'h877325dc_10575553_13841576_0c8f3981_7482808c_0852712d_38725173_71802e8f; +defparam bootram.RAM2.INIT_02=256'h2b700982_0c518172_a8057571_842980f3_269f3871_73527187_04ff3d0d_38873d0d; +defparam bootram.RAM2.INIT_03=256'h81e0c40c_22747008_0d029205_0404ff3d_52833d0d_880c5351_72068280_80880870; +defparam bootram.RAM2.INIT_04=256'h802ef338_06515170_a0087084_cc0c81b8_810b81e0_04803d0d_0c833d0d_5281e0c8; +defparam bootram.RAM2.INIT_05=256'h54527280_08708106_0d81b8a0_0c04fe3d_7181e0c0_0d04de3f_cc0c823d_820b81e0; +defparam bootram.RAM2.INIT_06=256'h5271802e_70810651_3971812a_8080529a_0c535381_71902a71_b8a00875_2e933881; +defparam bootram.RAM2.INIT_07=256'h7080c006_81b8a008_04803d0d_0c843d0d_72527180_3fff9e3f_ec51f8d3_8b3880df; +defparam bootram.RAM2.INIT_08=256'h0781e0cc_70902b88_028e0522_04ff3d0d_0c823d0d_80800b80_2ef23881_51517080; +defparam bootram.RAM2.INIT_09=256'h0d755480_0d04fd3d_cc0c833d_840b81e0_802ef338_06515170_a0087090_0c5281b8; +defparam bootram.RAM2.INIT_0A=256'h853d0d04_7327e638_81135385_52a6ff3f_14703352_f7a53f72_8638ba51_5372802e; +defparam bootram.RAM2.INIT_0B=256'h3d0d04f6_80ed3f87_80dff051_70335356_81113354_82113355_83113356_fb3d0d77; +defparam bootram.RAM2.INIT_0C=256'h3875802e_7680258f_5d5b5957_2a515b5f_7030709f_05bb0533_61630290_3d0d7c7e; +defparam bootram.RAM2.INIT_0D=256'h3f800851_7651aec5_80537752_79557854_77269438_76305777_ad51782d_8a387952; +defparam bootram.RAM2.INIT_0E=256'h8b053351_803d0d02_8c3d0d04_3351782d_80dffc05_dd3f8008_527651ae_ffbd3f77; +defparam bootram.RAM2.INIT_0F=256'h06575775_337081ff_5c5a5878_5208a3d8_70708405_3d0d8c3d_3d0d04f7_f68d3f82; +defparam bootram.RAM2.INIT_10=256'h2e80fb38_597580f0_19703357_80db3881_2e098106_065675a5_387681ff_802e81d1; +defparam bootram.RAM2.INIT_11=256'h80e42e80_81953975_2e819e38_8a387580_7580e324_e32eb938_a0387580_7580f024; +defparam bootram.RAM2.INIT_12=256'h80f82eba_80f53975_2e80db38_387580f3_80f5248b_2eac3875_397580f5_c638818b; +defparam bootram.RAM2.INIT_13=256'h59568055_19710852_da397784_51792d80_56805275_12335259_77841983_3880ec39; +defparam bootram.RAM2.INIT_14=256'h19710852_92397784_81538a52_55a3d854_52595680_84197108_53903977_a3d85480; +defparam bootram.RAM2.INIT_15=256'h5675802e_59567633_19710859_9e397784_51fdd03f_53905275_a3d85480_59568055; +defparam bootram.RAM2.INIT_16=256'h048a0b81_0c8b3d0d_39800b80_1959fea3_2dec3981_58335179_76708105_8e388052; +defparam bootram.RAM2.INIT_17=256'h04fc3d0d_38823d0d_515170ef_70810651_8c2a8132_b8b40870_803d0d81_e0d00c04; +defparam bootram.RAM2.INIT_18=256'h0a075272_86387181_5570802e_55555654_07728106_72982b7b_059b0533_797b0288; +defparam bootram.RAM2.INIT_19=256'h7181e0d4_51ffa93f_79712b51_52a07531_71820a07_802e8638_06515170_822a7081; +defparam bootram.RAM2.INIT_1A=256'hfc3d0d76_863d0d04_5170800c_81b88008_38ff953f_73802e89_d80c7351_0c7081e0; +defparam bootram.RAM2.INIT_1B=256'h2a517080_ee397190_15555351_22730581_72101570_74278f38_55805372_787a5455; +defparam bootram.RAM2.INIT_1C=256'h5280e988_0d865375_0d04fd3d_800c863d_52ec3971_72902a05_83ffff06_2e8d3871; +defparam bootram.RAM2.INIT_1D=256'h8812ff12_5180720c_e9985289_ff3d0d80_853d0d04_e9900c54_76700880_51b0983f; +defparam bootram.RAM2.INIT_1E=256'h5472742e_52527022_0b80e994_05225380_3d0d0296_3d0d04fd_25f33883_52527080; +defparam bootram.RAM2.INIT_1F=256'h83ffff06_0d787a71_0d04fa3d_800c853d_38805170_897225ee_88125252_8e388112; +defparam bootram.RAM2.INIT_20=256'h55555573_0b80e994_0880e998_0cad3980_80088405_2e893876_3f800880_535856c7; +defparam bootram.RAM2.INIT_21=256'h84140c88_75732376_389dad3f_897525eb_88145455_8f388115_5271802e_08881555; +defparam bootram.RAM2.INIT_22=256'h913ddc05_3d880552_3f735392_5254aee7_923dd605_54933d53_3d0d8670_3d0d04f1; +defparam bootram.RAM2.INIT_23=256'h8c3d2381_0523800b_028405a6_8b3d2380_818a800b_05a20523_90800284_51aed83f; +defparam bootram.RAM2.INIT_24=256'h8a52913d_665e8053_0523685d_028405ae_8d3d2380_80c0910b_05aa0523_80800284; +defparam bootram.RAM2.INIT_25=256'h23800b91_8405ba05_963d2202_22903d23_0523983d_028405ae_b73f8008_e40551fd; +defparam bootram.RAM2.INIT_26=256'h913d0d04_519fb03f_81e68405_6980c029_3dd40552_23ac5391_8405be05_3d238002; +defparam bootram.RAM2.INIT_27=256'h529a3df8_5380e988_adc53f86_3df20551_9b3d529a_3d238653_5b800b97_e83d0d80; +defparam bootram.RAM2.INIT_28=256'h9b3dc411_585a800b_80088008_23f7e23f_0580e205_05220284_3f0280f2_0551adb7; +defparam bootram.RAM2.INIT_29=256'h8305fc06_5fa33d08_5ea13d08_5c905d6e_08465984_0845a33d_6e44a13d_43f00543; +defparam bootram.RAM2.INIT_2A=256'h0c750854_84387376_55737527_3151565a_31908071_701a787c_84587508_408c3d56; +defparam bootram.RAM2.INIT_2B=256'he63f7508_e09851ef_2e883880_06547380_94160883_54738c38_38738306_73802e9a; +defparam bootram.RAM2.INIT_2C=256'hbf268438_ffac3878_57778025_17ff1959_84055708_823f7570_5276519e_53941608; +defparam bootram.RAM2.INIT_2D=256'h7f1f9405_0b943d23_40818a80_0d6b6e40_0d04ea3d_e83f9a3d_822a51f6_80c05978; +defparam bootram.RAM2.INIT_2E=256'h075a7996_6980c080_80ce0523_80028405_3d238180_23800b95_0580ca05_5a790284; +defparam bootram.RAM2.INIT_2F=256'h3f800809_525cfae0_52933d70_4780538a_90084668_052380e9_840580d2_3d238002; +defparam bootram.RAM2.INIT_30=256'h79923880_81ff065a_873f8008_535c5e8c_53983d70_23913d70_0580d205_5a790284; +defparam bootram.RAM2.INIT_31=256'h7b549080_575d9455_5960586b_027f5a6d_d53fa939_f6b63fed_c23f7a51_e0c451f7; +defparam bootram.RAM2.INIT_32=256'hf73d0d7f_983d0d04_38fd893f_867c26ef_34811c5c_5b79337b_1d7c1f5b_53805c7b; +defparam bootram.RAM2.INIT_33=256'ha6052377_80028405_768b3d23_23881857_8405a205_8d3d2202_228a3d23_5802ae05; +defparam bootram.RAM2.INIT_34=256'h23908002_810b8e3d_04ee3d0d_3f8b3d0d_7d51fe9e_05539152_548b3df8_567e5588; +defparam bootram.RAM2.INIT_35=256'h53800852_eb8c3f86_05b60523_34810284_8405b505_3d348402_23860b8f_8405b205; +defparam bootram.RAM2.INIT_36=256'h943df605_86538052_51a9e43f_943df205_53800852_eb863f84_51a9f43f_943dec05; +defparam bootram.RAM2.INIT_37=256'h53805b7a_05549086_55943de4_5780569c_59805880_5a025c80_64700844_51aaf13f; +defparam bootram.RAM2.INIT_38=256'h0b8e3d23_ee3d0d81_943d0d04_38fbcd3f_867b26ef_34811b5b_901b337a_1c5a80e0; +defparam bootram.RAM2.INIT_39=256'h893f8653_b60523ea_81028405_05b50534_34840284_860b8f3d_05b20523_90800284; +defparam bootram.RAM2.INIT_3A=256'h53805294_a8e13f86_3df20551_80085294_833f8453_a8f13fea_3dec0551_80085294; +defparam bootram.RAM2.INIT_3B=256'he4055490_9c55943d_80578056_80598058_0843025c_e73f8008_a9ee3fe9_3df60551; +defparam bootram.RAM2.INIT_3C=256'h04d83d0d_3f943d0d_ef38fac8_5b867b26_7a34811b_e0901b33_7a1c5a80_8653805b; +defparam bootram.RAM2.INIT_3D=256'h5c799b26_29f2055b_ad3d0884_cc38901d_09810682_7e90862e_1122405d_ab3d088e; +defparam bootram.RAM2.INIT_3E=256'h225a7990_9138821c_09810687_5a79812e_9d397b22_f49d3f87_80e0f451_8d387952; +defparam bootram.RAM2.INIT_3F=256'h2e098106_225a7982_f538861c_09810686_798c842e_841c225a_06878338_802e0981; +defparam bootram.RAM3.INIT_00=256'h79527a51_51a7a03f_981d5279_3d5a8653_a7ad3fa8_1d527a51_5b84539e_a238943d; +defparam bootram.RAM3.INIT_01=256'h5b888c3f_a81d7052_4088943f_9e1d7052_0686bb38_812e0981_1c225a79_87953f86; +defparam bootram.RAM3.INIT_02=256'h5a865380_9138a83d_5e800886_f63f8008_a40551a5_52aa3dff_5380e990_80084384; +defparam bootram.RAM3.INIT_03=256'h34851c33_1c33a33d_82052384_02840581_23821c22_7b22a23d_51a6d43f_e9885279; +defparam bootram.RAM3.INIT_04=256'h70547b53_a6a13f84_3de40551_537952aa_86052386_02840581_85053482_02840581; +defparam bootram.RAM3.INIT_05=256'haa3df405_79537f52_51a6843f_981d527a_055b8653_3f028192_525aa693_ab3dea05; +defparam bootram.RAM3.INIT_06=256'haa3ddc05_575d9c55_597e587e_027e5a7e_51a5ec3f_537a527f_9f3d4086_51a5f83f; +defparam bootram.RAM3.INIT_07=256'h397e9080_e73f84ee_26ef38f7_1c5c867c_337b3481_1d5b5b79_5c7b1d60_547e537d; +defparam bootram.RAM3.INIT_08=256'h2a708f06_d1387988_09810684_5b60842e_8c2a435b_1d702270_84e43890_2e098106; +defparam bootram.RAM3.INIT_09=256'he0905282_5e865380_84b4387e_ff065f7e_1b2280ff_84c03886_2e098106_515a7985; +defparam bootram.RAM3.INIT_0A=256'h08833881_a3ed3f80_70535b5c_80e99054_901c6255_38815e7e_3f800883_1d51a483; +defparam bootram.RAM3.INIT_0B=256'h5d407f81_22ec1140_1b33821c_84c53f89_529c1d51_8138881d_7b802e84_5c7d8738; +defparam bootram.RAM3.INIT_0C=256'h7a2e8f38_5d42407d_8411225d_7a08a41f_388c1b08_810683de_7f912e09_2e81bb38; +defparam bootram.RAM3.INIT_0D=256'h08428008_f4913f80_22535d5d_e41d821d_bd39ac1d_f0bd3f83_80e19451_79537d52; +defparam bootram.RAM3.INIT_0E=256'h3d408853_a3e13f9d_7d527951_5f5a8853_9b3d9a3d_3d237f4a_387a229a_802e83a6; +defparam bootram.RAM3.INIT_0F=256'h88537952_51a3c03f_b4055279_53aa3dff_23604888_1b22983d_a3d53f82_79527f51; +defparam bootram.RAM3.INIT_10=256'h7c26ef38_811c5c88_79337b34_7c1f5b5b_5e5c7b1d_557e843d_3f7b567c_7d51a3b7; +defparam bootram.RAM3.INIT_11=256'had398c1b_5a792d82_61840508_7b26ef38_811b5b88_84051c34_5a793302_805b7f1b; +defparam bootram.RAM3.INIT_12=256'h2e098106_335a7983_9539811a_81bb3882_387d882e_7d832e8a_33405b42_08a41e70; +defparam bootram.RAM3.INIT_13=256'h3f800841_2251f2cf_81f4387c_2e098106_5e5c7991_8912335c_1d80c01e_81a238ac; +defparam bootram.RAM3.INIT_14=256'h7d51a29b_88537a52_9c3d5c5e_794c993d_229c3d23_1c085a7c_80fe388c_8008802e; +defparam bootram.RAM3.INIT_15=256'h3dcc0552_4e8853aa_9e3d2379_5a821d22_3f901c08_7f51a28f_88537d52_3f973d40; +defparam bootram.RAM3.INIT_16=256'h5b79337b_1d7c1f5b_3d5e5c7b_7e557e84_ee3f7e56_527d51a1_3f88537a_7a51a1f7; +defparam bootram.RAM3.INIT_17=256'h38608405_887b26ef_34811b5b_0284051c_1b5a7933_38805b7f_887c26ef_34811c5c; +defparam bootram.RAM3.INIT_18=256'hd105347e_02840580_963d347e_1d5d5d7e_39ac1de4_e63f80de_80e951e3_085a792d; +defparam bootram.RAM3.INIT_19=256'h3d70525b_53605295_d605237e_02840580_23861a22_1a22973d_d2052384_02840580; +defparam bootram.RAM3.INIT_1A=256'h567c557d_d205237b_02840580_08095a79_f08e3f80_2a527c51_08537b81_f09a3f80; +defparam bootram.RAM3.INIT_1B=256'h3d0d800b_e80c04fc_800b80e9_80e9e40c_0d04800b_c53faa3d_526151f4_547a537f; +defparam bootram.RAM3.INIT_1C=256'h2e098106_53517075_71088c13_ec545651_700880e9_27a43876_55537274_80e9e408; +defparam bootram.RAM3.INIT_1D=256'h71535755_3d0d7779_3d0d04fb_70800c86_e738ff51_53737326_8b398113_85387251; +defparam bootram.RAM3.INIT_1E=256'he9e80881_0c8e3980_1480e9e4_26893881_08547387_3880e9e4_088025ba_ffb93f80; +defparam bootram.RAM3.INIT_1F=256'he9f01451_53755280_0c515486_80e9ec12_822b7608_73101470_e9e80c54_11870680; +defparam bootram.RAM3.INIT_20=256'hfd3d0d75_873d0d04_519fa43f_80e9f005_52738429_54865375_10800805_94398008; +defparam bootram.RAM3.INIT_21=256'h5276519e_80e9f005_53738429_08055486_80081080_08249938_80547380_51fed83f; +defparam bootram.RAM3.INIT_22=256'h14337088_902b0782_71982b71_33811233_3d0d7570_3d0d04fd_73800c85_fa3f8154; +defparam bootram.RAM3.INIT_23=256'h22565957_7f80eacc_f93d0d7d_853d0d04_54565452_800c5253_16337107_2b720783; +defparam bootram.RAM3.INIT_24=256'h902980ea_90291470_80d33873_54738326_72315256_8b3d2270_83ffff06_76a83873; +defparam bootram.RAM3.INIT_25=256'h38749029_748326ad_31575754_3d227072_ffff068d_c0397383_76742380_d0055154; +defparam bootram.RAM3.INIT_26=256'h33535474_38751770_75782791_ea3f8056_d005519d_902980ea_8a3d5273_15548853; +defparam bootram.RAM3.INIT_27=256'hd0545480_800b80ea_80eacc23_029a0522_04fc3d0d_39893d0d_811656ec_51e1de3f; +defparam bootram.RAM3.INIT_28=256'h14829014_eddc3f81_22740551_5280eacc_140cb8f4_800b828c_8288140c_7323800b; +defparam bootram.RAM3.INIT_29=256'h06515675_81327081_5c847c2c_80ead05a_3d0d800b_3d0d04f4_27d93886_54548374; +defparam bootram.RAM3.INIT_2A=256'h08ff2e80_e1a33f80_055b7b51_38781a88_ff2680d6_5b5d7981_82881a08_81be3875; +defparam bootram.RAM3.INIT_2B=256'h58587680_53515951_71802507_30728025_728d3270_8a327030_81ff0670_c5388008; +defparam bootram.RAM3.INIT_2C=256'h811a5a81_828c1a0c_1a0c800b_81058288_82881908_81055d34_5d777b70_2e833881; +defparam bootram.RAM3.INIT_2D=256'h568b7627_828c1b0c_19088111_9138828c_80d2387c_1908802e_b1388288_ff7a27ff; +defparam bootram.RAM3.INIT_2E=256'h57577533_771a781a_833d5b58_1954800b_19085588_ab388288_5675802e_bf387822; +defparam bootram.RAM3.INIT_2F=256'h828c1a0c_1a0c800b_800b8288_51f0e93f_cc227c05_ef3880ea_58887826_77348118; +defparam bootram.RAM3.INIT_30=256'h685194ba_5780c052_883d7054_04ea3d0d_388e3d0d_7c27fea9_1a5a5c83_811c8290; +defparam bootram.RAM3.INIT_31=256'h94387416_2e098106_387381aa_81ff2e9d_33515473_55741770_059d0557_3f800284; +defparam bootram.RAM3.INIT_32=256'h800c983d_38805473_be7527d1_39811555_3881548b_09810685_7381992e_70335154; +defparam bootram.RAM3.INIT_33=256'hca3f8008_52735199_5380e1b8_3f805584_795193ea_54548452_0d863d70_0d04f93d; +defparam bootram.RAM3.INIT_34=256'h3f8ac23f_3d0d8dd7_940c04fc_810b81e0_893d0d04_5574800c_06833881_752e0981; +defparam bootram.RAM3.INIT_35=256'he1bc5181_73883880_06515154_8d2a7081_b8b40870_89c13f81_06558051_800881ff; +defparam bootram.RAM3.INIT_36=256'h51dd843f_3880e2a0_08802e9a_febf3f80_b0800a51_51dd983f_3880e1f4_833974b5; +defparam bootram.RAM3.INIT_37=256'h51fee33f_3998800a_d85180cc_b53f80e2_800a5184_e1b73fb0_3f82ac51_81518987; +defparam bootram.RAM3.INIT_38=256'h80e3d051_5192bf3f_5298800a_5380ffff_3f838080_a451dcd7_bb3880e3_8008802e; +defparam bootram.RAM3.INIT_39=256'he93f8839_3f805183_ac51e0e9_dcb13f82_80e3f451_3ffee53f_ac51e0f9_dcc13f82; +defparam bootram.RAM3.INIT_3A=256'he5893fa0_e4fc5254_75705380_04fd3d0d_80f3900c_3d0d0471_dc9d3f86_80e4b051; +defparam bootram.RAM3.INIT_3B=256'h528051da_fe3d0da0_853d0d04_7351722d_802e8538_90085372_cc3f80f3_52a051da; +defparam bootram.RAM3.INIT_3C=256'hff0b8008_51898d3f_fc3d0d9a_843d0d04_8051722d_802e8538_90085372_b03f80f3; +defparam bootram.RAM3.INIT_3D=256'h7182802e_5580e454_86800653_820b8008_2e80ec38_81557180_06515354_862a7081; +defparam bootram.RAM3.INIT_3E=256'h845188c8_8338ff54_7184802e_3987e854_2e8e388a_8a547180_80248a38_9b387182; +defparam bootram.RAM3.INIT_3F=256'h7080f39c_e5f41133_06720780_8a2c7083_8c068008_3f71882a_855188c0_3f800852; +defparam bootram.RAM4.INIT_00=256'h80f39408_dac93f74_11085252_0680e888_71822b8c_52dab03f_55535154_0c80e5b4; +defparam bootram.RAM4.INIT_01=256'h2e098106_9e397482_38fec13f_098106a3_3874812e_74822ea6_80f3940c_2e983874; +defparam bootram.RAM4.INIT_02=256'h863d0d04_5187cd3f_fdfb3f99_a73f7351_f3980cfe_8e387380_f398082e_96387380; +defparam bootram.RAM4.INIT_03=256'h3f8d5298_995187ac_80f3980c_940cff0b_800b80f3_5187a23f_e13f8008_fd3d0dd7; +defparam bootram.RAM4.INIT_04=256'h908007f4_8f3f8008_3f845187_8451dfb1_3fbf9452_9c5187cd_81ae8052_5187d63f; +defparam bootram.RAM4.INIT_05=256'hcc51e2a7_735280e5_38800853_80082e8d_86fa3f73_b03f8451_54845187_9f067053; +defparam bootram.RAM4.INIT_06=256'h70852a82_02970533_04fd3d0d_3f853d0d_80518789_84800752_e33f8008_3f805186; +defparam bootram.RAM4.INIT_07=256'h71730707_832ba006_10900674_73070773_2a880671_84067281_0771832a_0671872a; +defparam bootram.RAM4.INIT_08=256'h51555255_0c515253_0682c080_077081ff_0778872b_c0067072_76852b80_7081ff06; +defparam bootram.RAM4.INIT_09=256'h983f81aa_81ff51ff_51ff9e3f_075381ff_0681d00a_0d74d00a_0d04fe3d_5552853d; +defparam bootram.RAM4.INIT_0A=256'h5252fef5_7081ff06_3f72882a_e151ff81_ff873f80_8c3fb251_819951ff_51ff923f; +defparam bootram.RAM4.INIT_0B=256'h902a7081_fedb3f72_72982a51_51fee23f_e83f8181_3fb251fe_0651feed_3f7281ff; +defparam bootram.RAM4.INIT_0C=256'ha051feb5_51feba3f_febf3f8e_c43f8051_81a151fe_51feca3f_fecf3fb0_ff065253; +defparam bootram.RAM4.INIT_0D=256'h05538052_54873dfc_fb3d0d82_843d0d04_51fea63f_feab3f80_b03fa051_3f8051fe; +defparam bootram.RAM4.INIT_0E=256'h12085859_d73d0884_d53d0880_b23d0d80_3d0d04ff_22800c87_ce3f863d_80d05183; +defparam bootram.RAM4.INIT_0F=256'h2681b238_16567596_bc39ff9f_dff53f81_80e68451_53829452_26903877_57778293; +defparam bootram.RAM4.INIT_10=256'h0b81e2cc_e18c0c81_5e810b81_3f800808_c15cd4c0_75080480_e6d00556_75842980; +defparam bootram.RAM4.INIT_11=256'hfef63f80_5c80f839_085f80c6_8c9d3f80_3f80085e_8a398c99_e4d00c81_0c800b81; +defparam bootram.RAM4.INIT_12=256'hc55c80d3_89f53f80_80f3c851_8c170852_90170853_5c80e839_065e80d6_0883ffff; +defparam bootram.RAM4.INIT_13=256'h39941753_80c25cb7_c45cbc39_2e863880_06567580_800881ff_518aba3f_3980f3c8; +defparam bootram.RAM4.INIT_14=256'h1708518b_1708528c_80055390_80d03dfe_d75ca439_88dc3f80_8c170851_90170852; +defparam bootram.RAM4.INIT_15=256'h54800b83_3dfdec05_945580d0_39a05c82_fcf83f83_d35c8051_5c8d3980_b93f80d2; +defparam bootram.RAM4.INIT_16=256'he6fe3f80_83808251_7826ec38_81185888_75337734_79055757_1980d23d_3d5a5877; +defparam bootram.RAM4.INIT_17=256'h05ab0533_05330284_3d0d02a7_83973ff9_ce3fff51_e7ac51d4_803d0d80_d03d0d04; +defparam bootram.RAM4.INIT_18=256'h7f7f5a57_3d0d7a7c_3d0d04f8_dfeb3f89_81528051_98547553_57578255_71882b07; +defparam bootram.RAM4.INIT_19=256'h8405a105_05583302_34767081_54738a3d_75811757_7425b738_16565480_575874ff; +defparam bootram.RAM4.INIT_1A=256'h802e8538_d8c73f73_06548a51_800881ff_51d7993f_7781ff06_3dfc0552_3482538a; +defparam bootram.RAM4.INIT_1B=256'h883d3481_38dc5675_de567483_05335580_3d0d02a3_3d0d04fa_73800c8a_c1398154; +defparam bootram.RAM4.INIT_1C=256'h893d3481_02ab0533_3d0d7c57_3d0d04f9_ff893f88_5280d051_055381f7_54883dfc; +defparam bootram.RAM4.INIT_1D=256'h38807725_73802e9e_06705654_800881ff_56d6b93f_05337052_055202a7_53893dfc; +defparam bootram.RAM4.INIT_1E=256'h0c893d0d_81557480_802e8338_70565473_0881ff06_d4fc3f80_7b527551_97387653; +defparam bootram.RAM4.INIT_1F=256'h80de2e09_33565674_800b883d_51ffa03f_f75280d0_fc055381_8154883d_04fa3d0d; +defparam bootram.RAM4.INIT_20=256'h81c0ac0c_800ca60b_eb0b81c0_c0940c80_04990b81_0c883d0d_81567580_81068338; +defparam bootram.RAM4.INIT_21=256'hc0a00c81_51820b81_81c0980c_06708107_882bbe80_803d0d72_c0b00c04_89b00b81; +defparam bootram.RAM4.INIT_22=256'h72882bbe_04803d0d_0c823d0d_c0a80880_70f13881_06515151_812a7081_c0a40870; +defparam bootram.RAM4.INIT_23=256'h70810651_0870812a_0c81c0a4_0b81c0a0_c09c0c84_0c517381_0781c098_80067081; +defparam bootram.RAM4.INIT_24=256'h83065271_71913875_55555757_7c728306_3d0d787a_04ff39fa_38823d0d_515170f1; +defparam bootram.RAM4.INIT_25=256'h822b7711_27943873_55557375_72822a72_5188ca3f_2e863881_06527180_8a387283; +defparam bootram.RAM4.INIT_26=256'h80e7b811_2a708f06_0d747084_0d04fe3d_e939883d_52811454_720c5254_77127008; +defparam bootram.RAM4.INIT_27=256'h82e09008_04803d0d_3f843d0d_5253cffb_e7b81133_728f0680_53d0883f_33545153; +defparam bootram.RAM4.INIT_28=256'h8c800607_80ff067a_93053378_fe3d0d02_823d0d04_5170f138_81065151_70882a70; +defparam bootram.RAM4.INIT_29=256'h82e0900c_e0800c71_f1387682_51515170_2a708106_90087088_535382e0_80c08007; +defparam bootram.RAM4.INIT_2A=256'h882a7081_e0900870_2e963882_72517280_82e0900c_71828007_82e0980c_7581ff06; +defparam bootram.RAM4.INIT_2B=256'h88805588_82e0940c_3d0d810b_3d0d04fc_70800c84_e0800851_70f13882_06515151; +defparam bootram.RAM4.INIT_2C=256'h51fef13f_53815281_90548a80_0d888055_0d04fc3d_873f863d_528051ff_54805380; +defparam bootram.RAM4.INIT_2D=256'h863d0d04_51fed53f_53815280_55885486_3d0d8880_3d0d04fc_06800c86_800881ff; +defparam bootram.RAM4.INIT_2E=256'h70802ef4_81ff0651_eb3f8008_04803d0d_0c823d0d_32810680_3f800881_803d0dca; +defparam bootram.RAM4.INIT_2F=256'h5475fe9b_888055a0_3fffb43f_269b38dd_3f758008_775684e3_04fb3d0d_38823d0d; +defparam bootram.RAM4.INIT_30=256'h08ff1156_0880cb3d_0d80c93d_04ffba3d_3f873d0d_8051fe84_07538152_0a069b0a; +defparam bootram.RAM4.INIT_31=256'hff52883d_82805381_2681a738_3f738008_1754849f_81b43875_7381ff26_57578055; +defparam bootram.RAM4.INIT_32=256'h82e0980c_fd9f3f74_3ffed43f_ea3ffefd_5273518a_80cb3d08_8f3f7553_7052548c; +defparam bootram.RAM4.INIT_33=256'h0b82e090_980c88a0_810b82e0_82e0800c_80c00a07_fec00a06_e0900c76_88800b82; +defparam bootram.RAM4.INIT_34=256'h84157008_8c0c54fe_700882e0_56fe8015_c83d558f_fcef3f80_82e0900c_0c8aa00b; +defparam bootram.RAM4.INIT_35=256'h82e0900c_5488800b_82e0800c_8c157008_840c54fe_700882e0_54fe8815_82e0880c; +defparam bootram.RAM4.INIT_36=256'h81557480_82e0980c_bc38800b_758025ff_90165656_b03fff16_e0900cfc_8a800b82; +defparam bootram.RAM4.INIT_37=256'hcb388157_80082680_3f805773_565682db_7212575a_0d797b7d_0d04f93d_0c80c83d; +defparam bootram.RAM4.INIT_38=256'h76547753_75278338_75555776_82807431_802ea238_ff065473_c3387581_74802e80; +defparam bootram.RAM4.INIT_39=256'he1388280_82807527_8e387454_5674802e_76315759_16741976_fdeb3f73_73527551; +defparam bootram.RAM4.INIT_3A=256'h38731354_73802e8d_7a565455_3d0d7678_3d0d04fc_76800c89_8c3f8157_54dc39fd; +defparam bootram.RAM4.INIT_3B=256'h08307074_81cb3f80_750ca639_84160c80_160c800b_38800b88_08742790_81ed3f80; +defparam bootram.RAM4.INIT_3C=256'h3f863d0d_7151fcc9_7188160c_0684160c_72760c74_3f800830_515281bd_06ff1656; +defparam bootram.RAM4.INIT_3D=256'h15082e94_88140884_9f388153_5271802e_ff067054_3f800881_7554fc98_04fd3d0d; +defparam bootram.RAM4.INIT_3E=256'h3d0d8880_3d0d04fc_72800c85_943f8053_160c51fc_08057088_88140880_3881823f; +defparam bootram.RAM4.INIT_3F=256'h0d80f3a0_0d04ff3d_800c863d_fe800a06_a33f8008_528151fa_f90a5381_55a05481; +defparam bootram.RAM5.INIT_00=256'h387180f3_09810693_5170a02e_ff065451_06800881_2a7081ff_3f800888_08a038d7; +defparam bootram.RAM5.INIT_01=256'h0880e882_04c03f80_0c833d0d_b33f7180_278438f5_52528271_a008ea11_a00c80f3; +defparam bootram.RAM5.INIT_02=256'h0d7d56f9_0c04f63d_80082b80_a93f810b_800c04ff_0b80082b_04f33f81_0533800c; +defparam bootram.RAM5.INIT_03=256'h810b82e0_82e0800c_0c7c882b_0b82e084_e0900c8b_88800b82_82e0980c_983f800b; +defparam bootram.RAM5.INIT_04=256'h3888800b_762780d3_55805473_f8e73f7e_82e0900c_0c8aa80b_0b82e090_980c88a8; +defparam bootram.RAM5.INIT_05=256'h5a82e080_82e08408_e0880859_8c085882_cc3f82e0_e0900cf8_8a800b82_82e0900c; +defparam bootram.RAM5.INIT_06=256'h70337570_38711751_71732791_70538052_73278338_57905370_76753152_085b883d; +defparam bootram.RAM5.INIT_07=256'h7251f789_04803d0d_0c8c3d0d_0b82e098_ffa93980_39721454_811252ec_81055734; +defparam bootram.RAM5.INIT_08=256'h70800c54_de3f8008_05085182_528c0888_088c0508_0d80538c_8c0cfd3d_3f8c0802; +defparam bootram.RAM5.INIT_09=256'h82b93f80_88050851_08528c08_8c088c05_3d0d8153_028c0cfd_0c048c08_853d0d8c; +defparam bootram.RAM5.INIT_0A=256'h88050880_050c8c08_0b8c08fc_f93d0d80_08028c0c_8c0c048c_54853d0d_0870800c; +defparam bootram.RAM5.INIT_0B=256'h810b8c08_05088838_0c8c08fc_8c08f405_050c800b_308c0888_08880508_25ab388c; +defparam bootram.RAM5.INIT_0C=256'h8c088c05_8c050830_ab388c08_05088025_0c8c088c_8c08fc05_08f40508_f4050c8c; +defparam bootram.RAM5.INIT_0D=256'h08fc050c_f005088c_050c8c08_0b8c08f0_08883881_8c08fc05_08f0050c_0c800b8c; +defparam bootram.RAM5.INIT_0E=256'hfc050880_0c548c08_8c08f805_3f800870_085181a7_8c088805_8c050852_80538c08; +defparam bootram.RAM5.INIT_0F=256'h048c0802_3d0d8c0c_800c5489_f8050870_050c8c08_308c08f8_08f80508_2e8c388c; +defparam bootram.RAM5.INIT_10=256'h0888050c_0508308c_388c0888_08802593_8c088805_08fc050c_0d800b8c_8c0cfb3d; +defparam bootram.RAM5.INIT_11=256'h538c088c_8c050c81_08308c08_8c088c05_80258c38_088c0508_fc050c8c_810b8c08; +defparam bootram.RAM5.INIT_12=256'h388c08f8_08802e8c_8c08fc05_f8050c54_08708c08_51ad3f80_08880508_0508528c; +defparam bootram.RAM5.INIT_13=256'hfd3d0d81_08028c0c_8c0c048c_54873d0d_0870800c_8c08f805_08f8050c_0508308c; +defparam bootram.RAM5.INIT_14=256'hfc050880_ac388c08_88050827_05088c08_0c8c088c_8c08f805_050c800b_0b8c08fc; +defparam bootram.RAM5.INIT_15=256'h08108c08_8c08fc05_088c050c_0508108c_388c088c_05082499_0b8c088c_2ea33880; +defparam bootram.RAM5.INIT_16=256'h8c088805_0826a138_8c088805_088c0508_80c9388c_0508802e_398c08fc_fc050cc9; +defparam bootram.RAM5.INIT_17=256'h8c08fc05_08f8050c_0508078c_088c08fc_8c08f805_0888050c_0508318c_088c088c; +defparam bootram.RAM5.INIT_18=256'h802e8f38_08900508_ffaf398c_088c050c_08812a8c_8c088c05_08fc050c_08812a8c; +defparam bootram.RAM5.INIT_19=256'hf4050880_0c518c08_8c08f405_f8050870_8d398c08_f4050c51_08708c08_8c088805; +defparam bootram.RAM5.INIT_1A=256'h802eb038_83065170_38747407_8372278c_79565652_3d0d7877_8c0c04fc_0c853d0d; +defparam bootram.RAM5.INIT_1B=256'h54555571_8115ff14_bd388115_2e098106_52537271_74337433_ff2ea038_ff125271; +defparam bootram.RAM5.INIT_1C=256'h38841184_0981068f_0873082e_74545170_3d0d0474_0b800c86_06e23880_ff2e0981; +defparam bootram.RAM5.INIT_1D=256'h3d0d7670_3d0d04fc_31800c86_af397271_735555ff_26e93870_54517183_14fc1454; +defparam bootram.RAM5.INIT_1E=256'h98387270_5271ff2e_a738ff12_5170802e_75078306_278c3872_55558f72_797b5555; +defparam bootram.RAM5.INIT_1F=256'h74517270_863d0d04_3874800c_098106ea_5271ff2e_5634ff12_74708105_81055433; +defparam bootram.RAM5.INIT_20=256'h71708405_84055408_530c7270_71708405_84055408_530c7270_71708405_84055408; +defparam bootram.RAM5.INIT_21=256'h70840554_27953872_c9388372_52718f26_530cf012_71708405_84055408_530c7270; +defparam bootram.RAM5.INIT_22=256'h059f0533_7971028c_fc3d0d76_54ff8339_26ed3870_12527183_05530cfc_08717084; +defparam bootram.RAM5.INIT_23=256'h70810555_93387373_5271ff2e_a238ff12_5170802e_38748306_8372278a_57555355; +defparam bootram.RAM5.INIT_24=256'h2b075154_07707190_74882b75_3d0d0474_74800c86_8106ef38_71ff2e09_34ff1252; +defparam bootram.RAM5.INIT_25=256'h71708405_05530c72_72717084_8405530c_0c727170_70840553_a5387271_518f7227; +defparam bootram.RAM5.INIT_26=256'hf2387053_52718326_530cfc12_71708405_27903872_dd388372_52718f26_530cf012; +defparam bootram.RAM5.INIT_27=256'h2e80d438_06517080_71740783_2e80d938_55527280_7c705455_3d0d787a_ff9039fa; +defparam bootram.RAM5.INIT_28=256'h7081ff06_2e818738_a9387280_2e098106_56517471_71337433_ff2eb138_ff135372; +defparam bootram.RAM5.INIT_29=256'h56517081_71337433_8106d138_72ff2e09_15555552_128115ff_80fc3881_5170802e; +defparam bootram.RAM5.INIT_2A=256'h71087408_73278838_74575583_3d0d0471_70800c88_31515252_ff067171_ff067581; +defparam bootram.RAM5.INIT_2B=256'h70f88482_fdff1206_7009f7fb_b1387408_5372802e_9739fc13_765552ff_2e883874; +defparam bootram.RAM5.INIT_2C=256'h765552fe_2ed03874_74087608_7327d038_17575583_38841584_5151709a_81800651; +defparam bootram.RAM5.INIT_2D=256'hf3a40cff_9e387380_5472812e_e7e80854_0d800b80_0d04fd3d_800c883d_df39800b; +defparam bootram.RAM5.INIT_2E=256'hffad813f_80f3a40c_f6a33f72_3f800851_51ffb5b8_e89c5281_acba3f80_ad9e3fff; +defparam bootram.RAM5.INIT_2F=256'ha40bfc05_3d0d80e8_00ff39ff_51f6863f_9b3f8008_8151ffb5_80e89c52_ffac9d3f; +defparam bootram.RAM5.INIT_30=256'h0404ffad_38833d0d_098106f1_5270ff2e_12700852_38702dfc_70ff2e91_70085252; +defparam bootram.RAM5.INIT_31=256'h636b6574_6c207061_6e74726f_6e20636f_6f722069_21457272_00000040_ac3f0400; +defparam bootram.RAM5.INIT_32=256'h6c697479_74696269_6f6d7061_65642063_70656374_3a204578_646c6572_2068616e; +defparam bootram.RAM5.INIT_33=256'h6f722069_21457272_25640a00_676f7420_62757420_25642c20_62657220_206e756d; +defparam bootram.RAM5.INIT_34=256'h70656374_3a204578_646c6572_2068616e_636b6574_6c207061_6e74726f_6e20636f; +defparam bootram.RAM5.INIT_35=256'h74202564_7420676f_2c206275_68202564_656e6774_6164206c_61796c6f_65642070; +defparam bootram.RAM5.INIT_36=256'h203d2025_70656564_643a2073_616e6765_6b206368_206c696e_0a657468_0a000000; +defparam bootram.RAM5.INIT_37=256'h720a0000_6f616465_6f6f746c_44502062_31302055_50204e32_0a555352_640a0000; +defparam bootram.RAM5.INIT_38=256'h640a0000_723a2025_756d6265_7479206e_62696c69_70617469_20636f6d_46504741; +defparam bootram.RAM5.INIT_39=256'h723a2025_756d6265_7479206e_62696c69_70617469_20636f6d_77617265_4669726d; +defparam bootram.RAM5.INIT_3A=256'h7061636b_65727920_65636f76_69702072_476f7420_00000000_61646472_640a0000; +defparam bootram.RAM5.INIT_3B=256'h00000826_00000826_00000826_00000826_00000826_00000731_00000000_65743a20; +defparam bootram.RAM5.INIT_3C=256'h00000826_00000826_000007fc_00000826_00000826_00000776_0000078d_00000826; +defparam bootram.RAM5.INIT_3D=256'h000007cf_000007ca_000007c5_0000073e_000007aa_00000826_00000826_00000826; +defparam bootram.RAM5.INIT_3E=256'hffffff00_c0a80a01_c0a80a02_3fff0000_0050c285_000007ea_000007dd_000007d6; +defparam bootram.RAM5.INIT_3F=256'h30313233_2e256400_642e2564_25642e25_45000000_01b200d9_05160364_14580a2c; +defparam bootram.RAM6.INIT_00=256'h5f706b74_73656e64_ffff0000_ffffffff_00000000_43444546_38394142_34353637; +defparam bootram.RAM6.INIT_01=256'h72206275_6e642f6f_656e2061_6f66206c_656e7420_69676e6d_6420616c_3a206261; +defparam bootram.RAM6.INIT_02=256'h74206361_6f206869_65642074_6661696c_6f6e3a20_636f6d6d_6e65745f_66000000; +defparam bootram.RAM6.INIT_03=256'h6172703a_646c655f_0a68616e_00000000_666f7220_696e6720_6c6f6f6b_63686520; +defparam bootram.RAM6.INIT_04=256'h6e736973_696e636f_55445020_0a000000_3d202564_697a6520_72642073_20776569; +defparam bootram.RAM6.INIT_05=256'h53746172_0b0b0b0b_00000000_2025640a_3a202564_67746873_206c656e_74656e74; +defparam bootram.RAM6.INIT_06=256'h6164696e_2e204c6f_6d6f6465_61666520_696e2073_50322b20_20555352_74696e67; +defparam bootram.RAM6.INIT_07=256'h20666f72_6b696e67_43686563_00000000_6172652e_69726d77_66652066_67207361; +defparam bootram.RAM6.INIT_08=256'h2e2e2e00_6d616765_47412069_6e204650_6374696f_726f6475_69642070_2076616c; +defparam bootram.RAM6.INIT_09=256'h666f756e_61676520_4120696d_20465047_74696f6e_6f647563_64207072_56616c69; +defparam bootram.RAM6.INIT_0A=256'h616c6964_4e6f2076_742e0000_20626f6f_6720746f_7074696e_7474656d_642e2041; +defparam bootram.RAM6.INIT_0B=256'h2e0a4661_6f756e64_67652066_20696d61_46504741_696f6e20_64756374_2070726f; +defparam bootram.RAM6.INIT_0C=256'h726d7761_6e206669_6c742d69_20627569_6820746f_726f7567_67207468_6c6c696e; +defparam bootram.RAM6.INIT_0D=256'h6520666f_6d776172_20666972_74696f6e_6f647563_64207072_56616c69_72652e00; +defparam bootram.RAM6.INIT_0E=256'h64696e67_206c6f61_73686564_46696e69_2e2e2e00_64696e67_204c6f61_756e642e; +defparam bootram.RAM6.INIT_0F=256'h65747572_523a2052_4552524f_2e000000_6d616765_6e672069_61727469_2e205374; +defparam bootram.RAM6.INIT_10=256'h6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672; +defparam bootram.RAM6.INIT_11=256'h64756374_2070726f_616c6964_4e6f2076_6e210000_61707065_65722068_206e6576; +defparam bootram.RAM6.INIT_12=256'h7468726f_696e6720_46616c6c_6e642e20_20666f75_77617265_6669726d_696f6e20; +defparam bootram.RAM6.INIT_13=256'h53706565_2e000000_77617265_6669726d_2d696e20_75696c74_746f2062_75676820; +defparam bootram.RAM6.INIT_14=256'h58000000_57455f54_00000000_4e4f4e45_00000000_2025640a_7420746f_64207365; +defparam bootram.RAM6.INIT_15=256'h20666c6f_726e6574_65746865_43000000_45545249_53594d4d_58000000_57455f52; +defparam bootram.RAM6.INIT_16=256'h2077726f_4144563a_4e45475f_4155544f_5048595f_6c3a2000_6e74726f_7720636f; +defparam bootram.RAM6.INIT_17=256'h00000001_00030003_00000000_780a0000_20307825_20676f74_7825782c_74652030; +defparam bootram.RAM6.INIT_18=256'h68616e64_6b657420_20706163_64617465_6e207570_6f722069_21457272_00030203; +defparam bootram.RAM6.INIT_19=256'h2025642c_6e677468_64206c65_796c6f61_64207061_65637465_20457870_6c65723a; +defparam bootram.RAM6.INIT_1A=256'h00002261_000022b1_000022b1_0000220b_00000000_2025640a_20676f74_20627574; +defparam bootram.RAM6.INIT_1B=256'h000022b1_000022b1_000022b1_000022b1_000022b1_000022b1_0000222a_0000224c; +defparam bootram.RAM6.INIT_1C=256'h000022b1_000022a7_00002290_000022b1_000022b1_000022b1_000022b1_000022b1; +defparam bootram.RAM6.INIT_1D=256'h34353637_30313233_00000000_6f72740a_0a0a6162_0000227d_0000223c_000022b1; +defparam bootram.RAM6.INIT_1E=256'hffff00ff_ff00ffff_00ffffff_65000000_792e6578_64756d6d_43444546_38394142; +defparam bootram.RAM6.INIT_1F=256'hffff0031_05050400_01010100_0000342c_00000000_00000000_00000000_ffffff00; +defparam bootram.RAM6.INIT_20=256'h000033c8_10101200_000032a8_000032a0_00003298_00003290_000b0000_0018000f; +defparam bootram.RAM6.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_ffffffff_00000000_ffffffff; +defparam bootram.RAM6.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_37=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_38=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_00=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_02=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_03=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_04=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_06=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_37=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_38=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; diff --git a/fpga/usrp2/top/N2x0/capture_ddrlvds.v b/fpga/usrp2/top/N2x0/capture_ddrlvds.v new file mode 100644 index 000000000..e261dcbe8 --- /dev/null +++ b/fpga/usrp2/top/N2x0/capture_ddrlvds.v @@ -0,0 +1,55 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + + +module capture_ddrlvds + #(parameter WIDTH=7) + (input clk, + input ssclk_p, + input ssclk_n, + input [WIDTH-1:0] in_p, + input [WIDTH-1:0] in_n, + output reg [(2*WIDTH)-1:0] out); + + wire [WIDTH-1:0] ddr_dat; + wire ssclk; + wire [(2*WIDTH)-1:0] out_pre1; + reg [(2*WIDTH)-1:0] out_pre2; + + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) + clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); + + genvar i; + generate + for(i = 0; i < WIDTH; i = i + 1) + begin : gen_lvds_pins + IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("FALSE")) ibufds + (.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) ); + IDDR2 #(.DDR_ALIGNMENT("C1")) iddr2 + (.Q0(out_pre1[2*i]), .Q1(out_pre1[(2*i)+1]), .C0(ssclk), .C1(~ssclk), + .CE(1'b1), .D(ddr_dat[i]), .R(1'b0), .S(1'b0)); + end + endgenerate + + always @(posedge clk) + out_pre2 <= out_pre1; + + always @(posedge clk) + out <= out_pre2; + +endmodule // capture_ddrlvds diff --git a/fpga/usrp2/top/N2x0/u2plus.ucf b/fpga/usrp2/top/N2x0/u2plus.ucf new file mode 100755 index 000000000..5fbe55c26 --- /dev/null +++ b/fpga/usrp2/top/N2x0/u2plus.ucf @@ -0,0 +1,424 @@ +## Main 100 MHz Clock +NET "CLK_FPGA_P" LOC = "AA13" ; +NET "CLK_FPGA_N" LOC = "Y13" ; + +## ADC +NET "ADC_clkout_p" LOC = "P1" ; +NET "ADC_clkout_n" LOC = "P2" ; +NET "ADCA_12_p" LOC = "Y1" ; +NET "ADCA_12_n" LOC = "Y2" ; +NET "ADCA_10_p" LOC = "W3" ; +NET "ADCA_10_n" LOC = "W4" ; +NET "ADCA_8_p" LOC = "T7" ; +NET "ADCA_8_n" LOC = "U6" ; +NET "ADCA_6_p" LOC = "U5" ; +NET "ADCA_6_n" LOC = "V5" ; +NET "ADCA_4_p" LOC = "T10" ; +NET "ADCA_4_n" LOC = "T9" ; +NET "ADCA_2_p" LOC = "V1" ; +NET "ADCA_2_n" LOC = "V2" ; +NET "ADCA_0_p" LOC = "R8" ; +NET "ADCA_0_n" LOC = "R7" ; +NET "ADCB_2_p" LOC = "U7" ; +NET "ADCB_2_n" LOC = "U8" ; +NET "ADCB_0_p" LOC = "AA2" ; +NET "ADCB_0_n" LOC = "AA3" ; +NET "ADCB_4_p" LOC = "AE1" ; +NET "ADCB_4_n" LOC = "AE2" ; +NET "ADCB_6_p" LOC = "W1" ; +NET "ADCB_6_n" LOC = "W2" ; +NET "ADCB_8_p" LOC = "U3" ; +NET "ADCB_8_n" LOC = "V4" ; +NET "ADCB_10_p" LOC = "J1" ; +NET "ADCB_10_n" LOC = "K1" ; +NET "ADCB_12_p" LOC = "J3" ; +NET "ADCB_12_n" LOC = "J2" ; + +## DAC +NET "DAC_LOCK" LOC = "P4" ; +NET "DACA<0>" LOC = "P8" ; +NET "DACA<1>" LOC = "P9" ; +NET "DACA<2>" LOC = "R5" ; +NET "DACA<3>" LOC = "R6" ; +NET "DACA<4>" LOC = "P7" ; +NET "DACA<5>" LOC = "P6" ; +NET "DACA<6>" LOC = "T3" ; +NET "DACA<7>" LOC = "T4" ; +NET "DACA<8>" LOC = "R3" ; +NET "DACA<9>" LOC = "R4" ; +NET "DACA<10>" LOC = "R2" ; +NET "DACA<11>" LOC = "N1" ; +NET "DACA<12>" LOC = "N2" ; +NET "DACA<13>" LOC = "N5" ; +NET "DACA<14>" LOC = "N4" ; +NET "DACA<15>" LOC = "M2" ; +NET "DACB<0>" LOC = "M5" ; +NET "DACB<1>" LOC = "M6" ; +NET "DACB<2>" LOC = "M4" ; +NET "DACB<3>" LOC = "M3" ; +NET "DACB<4>" LOC = "M8" ; +NET "DACB<5>" LOC = "M7" ; +NET "DACB<6>" LOC = "L4" ; +NET "DACB<7>" LOC = "L3" ; +NET "DACB<8>" LOC = "K3" ; +NET "DACB<9>" LOC = "K2" ; +NET "DACB<10>" LOC = "K5" ; +NET "DACB<11>" LOC = "K4" ; +NET "DACB<12>" LOC = "M10" ; +NET "DACB<13>" LOC = "M9" ; +NET "DACB<14>" LOC = "J5" ; +NET "DACB<15>" LOC = "J4" ; + +## TX DB GPIO +NET "io_tx<15>" LOC = "K6" ; +NET "io_tx<14>" LOC = "L7" ; +NET "io_tx<13>" LOC = "H2" ; +NET "io_tx<12>" LOC = "H1" ; +NET "io_tx<11>" LOC = "L10" ; +NET "io_tx<10>" LOC = "L9" ; +NET "io_tx<9>" LOC = "G3" ; +NET "io_tx<8>" LOC = "F3" ; +NET "io_tx<7>" LOC = "K7" ; +NET "io_tx<6>" LOC = "J6" ; +NET "io_tx<5>" LOC = "E1" ; +NET "io_tx<4>" LOC = "F2" ; +NET "io_tx<3>" LOC = "J7" ; +NET "io_tx<2>" LOC = "H6" ; +NET "io_tx<1>" LOC = "F5" ; +NET "io_tx<0>" LOC = "G4" ; + +## RX DB GPIO +NET "io_rx<15>" LOC = "AD1" ; +NET "io_rx<14>" LOC = "AD2" ; +NET "io_rx<13>" LOC = "AC2" ; +NET "io_rx<12>" LOC = "AC3" ; +NET "io_rx<11>" LOC = "W7" ; +NET "io_rx<10>" LOC = "W6" ; +NET "io_rx<9>" LOC = "U9" ; +NET "io_rx<8>" LOC = "V8" ; +NET "io_rx<7>" LOC = "AB1" ; +NET "io_rx<6>" LOC = "AC1" ; +NET "io_rx<5>" LOC = "V7" ; +NET "io_rx<4>" LOC = "V6" ; +NET "io_rx<3>" LOC = "Y5" ; +NET "io_rx<2>" LOC = "R10" ; +NET "io_rx<1>" LOC = "R1" ; +NET "io_rx<0>" LOC = "M1" ; + +## MISC +NET "leds<5>" LOC = "AF25" ; +NET "leds<4>" LOC = "AE25" ; +NET "leds<3>" LOC = "AF23" ; +NET "leds<2>" LOC = "AE23" ; +NET "leds<1>" LOC = "AB18" ; +NET "FPGA_RESET" LOC = "K24" ; + +## Debug +NET "debug_clk<0>" LOC = "AA10" ; +NET "debug_clk<1>" LOC = "AD11" ; +NET "debug<0>" LOC = "AC19" ; +NET "debug<1>" LOC = "AF20" ; +NET "debug<2>" LOC = "AE20" ; +NET "debug<3>" LOC = "AC16" ; +NET "debug<4>" LOC = "AB16" ; +NET "debug<5>" LOC = "AF19" ; +NET "debug<6>" LOC = "AE19" ; +NET "debug<7>" LOC = "V15" ; +NET "debug<8>" LOC = "U15" ; +NET "debug<9>" LOC = "AE17" ; +NET "debug<10>" LOC = "AD17" ; +NET "debug<11>" LOC = "V14" ; +NET "debug<12>" LOC = "W15" ; +NET "debug<13>" LOC = "AC15" ; +NET "debug<14>" LOC = "AD14" ; +NET "debug<15>" LOC = "AC14" ; +NET "debug<16>" LOC = "AC11" ; +NET "debug<17>" LOC = "AB12" ; +NET "debug<18>" LOC = "AC12" ; +NET "debug<19>" LOC = "V13" ; +NET "debug<20>" LOC = "W13" ; +NET "debug<21>" LOC = "AE8" ; +NET "debug<22>" LOC = "AF8" ; +NET "debug<23>" LOC = "V12" ; +NET "debug<24>" LOC = "W12" ; +NET "debug<25>" LOC = "AB9" ; +NET "debug<26>" LOC = "AC9" ; +NET "debug<27>" LOC = "AC8" ; +NET "debug<28>" LOC = "AB7" ; +NET "debug<29>" LOC = "V11" ; +NET "debug<30>" LOC = "U11" ; +NET "debug<31>" LOC = "Y10" ; + +## UARTS +NET "TXD<3>" LOC = "AD20" ; +NET "TXD<2>" LOC = "AC20" ; +NET "TXD<1>" LOC = "AD19" ; +NET "RXD<3>" LOC = "AF17" ; +NET "RXD<2>" LOC = "AF15" ; +NET "RXD<1>" LOC = "AD12" ; + +## AD9510 +NET "clk_status" LOC = "AD22" ; +NET "CLK_FUNC" LOC = "AC21" ; +NET "clk_sel<0>" LOC = "AE21" ; +NET "clk_sel<1>" LOC = "AD21" ; +NET "clk_en<1>" LOC = "AA17" ; +NET "clk_en<0>" LOC = "Y17" ; + +## I2C +NET "SDA" LOC = "V16" ; +NET "SCL" LOC = "U16" ; + +## Timing +NET "PPS_IN" LOC = "AB6" ; +NET "PPS2_IN" LOC = "AA20" ; + +## SPI +NET "SEN_CLK" LOC = "AA18" ; +NET "MOSI_CLK" LOC = "W17" ; +NET "SCLK_CLK" LOC = "V17" ; +NET "MISO_CLK" LOC = "AC10" ; + +NET "SEN_DAC" LOC = "AE7" ; +NET "SCLK_DAC" LOC = "AF5" ; +NET "MOSI_DAC" LOC = "AE6" ; +NET "MISO_DAC" LOC = "Y3" ; + +NET "SCLK_ADC" LOC = "B1" ; +NET "MOSI_ADC" LOC = "J8" ; +NET "SEN_ADC" LOC = "J9" ; + +NET "MOSI_TX_ADC" LOC = "V10" ; +NET "SEN_TX_ADC" LOC = "W10" ; +NET "SCLK_TX_ADC" LOC = "AC6" ; +NET "MISO_TX_ADC" LOC = "G1" ; + +NET "MOSI_TX_DAC" LOC = "AD6" ; +NET "SEN_TX_DAC" LOC = "AE4" ; +NET "SCLK_TX_DAC" LOC = "AF4" ; + +NET "SCLK_TX_DB" LOC = "AE3" ; +NET "MOSI_TX_DB" LOC = "AF3" ; +NET "SEN_TX_DB" LOC = "W9" ; +NET "MISO_TX_DB" LOC = "AA5" ; + +NET "MOSI_RX_ADC" LOC = "E3" ; +NET "SCLK_RX_ADC" LOC = "F4" ; +NET "SEN_RX_ADC" LOC = "D3" ; +NET "MISO_RX_ADC" LOC = "C1" ; + +NET "SCLK_RX_DAC" LOC = "E4" ; +NET "SEN_RX_DAC" LOC = "K9" ; +NET "MOSI_RX_DAC" LOC = "K8" ; + +NET "SCLK_RX_DB" LOC = "G6" ; +NET "MOSI_RX_DB" LOC = "H7" ; +NET "SEN_RX_DB" LOC = "B2" ; +NET "MISO_RX_DB" LOC = "H4" ; + +## ETH PHY +NET "CLK_TO_MAC" LOC = "P26" ; + +NET "GMII_TXD<7>" LOC = "G21" ; +NET "GMII_TXD<6>" LOC = "C26" ; +NET "GMII_TXD<5>" LOC = "C25" ; +NET "GMII_TXD<4>" LOC = "J21" ; +NET "GMII_TXD<3>" LOC = "H21" ; +NET "GMII_TXD<2>" LOC = "D25" ; +NET "GMII_TXD<1>" LOC = "D24" ; +NET "GMII_TXD<0>" LOC = "E26" ; +NET "GMII_TX_EN" LOC = "D26" ; +NET "GMII_TX_ER" LOC = "J19" ; +NET "GMII_GTX_CLK" LOC = "J20" ; +NET "GMII_TX_CLK" LOC = "P25" ; + +NET "GMII_RX_CLK" LOC = "P21" ; +NET "GMII_RXD<7>" LOC = "G22" ; +NET "GMII_RXD<6>" LOC = "K19" ; +NET "GMII_RXD<5>" LOC = "K18" ; +NET "GMII_RXD<4>" LOC = "E24" ; +NET "GMII_RXD<3>" LOC = "F23" ; +NET "GMII_RXD<2>" LOC = "L18" ; +NET "GMII_RXD<1>" LOC = "L17" ; +NET "GMII_RXD<0>" LOC = "F25" ; +NET "GMII_RX_DV" LOC = "F24" ; +NET "GMII_RX_ER" LOC = "L20" ; +NET "GMII_CRS" LOC = "K20" ; +NET "GMII_COL" LOC = "G23" ; + +NET "PHY_INTn" LOC = "L22" ; +NET "MDIO" LOC = "K21" ; +NET "MDC" LOC = "J23" ; +NET "PHY_RESETn" LOC = "J22" ; +NET "ETH_LED" LOC = "H20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; + +## MIMO Interface +NET "exp_time_out_p" LOC = "Y14" ; +NET "exp_time_out_n" LOC = "AA14" ; +NET "exp_time_in_p" LOC = "N18" ; +NET "exp_time_in_n" LOC = "N17" ; +NET "exp_user_out_p" LOC = "AF14" ; +NET "exp_user_out_n" LOC = "AE14" ; +NET "exp_user_in_p" LOC = "L24" ; +NET "exp_user_in_n" LOC = "M23" ; + +## SERDES +NET "ser_enable" LOC = "R20" ; +NET "ser_prbsen" LOC = "U23" ; +NET "ser_loopen" LOC = "R19" ; +NET "ser_rx_en" LOC = "Y21" ; +NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK +NET "ser_t<15>" LOC = "V23" ; +NET "ser_t<14>" LOC = "U22" ; +NET "ser_t<13>" LOC = "V24" ; +NET "ser_t<12>" LOC = "V25" ; +NET "ser_t<11>" LOC = "W23" ; +NET "ser_t<10>" LOC = "V22" ; +NET "ser_t<9>" LOC = "T18" ; +NET "ser_t<8>" LOC = "T17" ; +NET "ser_t<7>" LOC = "Y24" ; +NET "ser_t<6>" LOC = "Y25" ; +NET "ser_t<5>" LOC = "U21" ; +NET "ser_t<4>" LOC = "T20" ; +NET "ser_t<3>" LOC = "Y22" ; +NET "ser_t<2>" LOC = "Y23" ; +NET "ser_t<1>" LOC = "U19" ; +NET "ser_t<0>" LOC = "U18" ; +NET "ser_tkmsb" LOC = "AA24" ; +NET "ser_tklsb" LOC = "AA25" ; +NET "ser_rx_clk" LOC = "P18" ; +NET "ser_r<15>" LOC = "V21" ; +NET "ser_r<14>" LOC = "U20" ; +NET "ser_r<13>" LOC = "AA22" ; +NET "ser_r<12>" LOC = "AA23" ; +NET "ser_r<11>" LOC = "V18" ; +NET "ser_r<10>" LOC = "V19" ; +NET "ser_r<9>" LOC = "AB23" ; +NET "ser_r<8>" LOC = "AC26" ; +NET "ser_r<7>" LOC = "AB26" ; +NET "ser_r<6>" LOC = "AD26" ; +NET "ser_r<5>" LOC = "AC25" ; +NET "ser_r<4>" LOC = "W20" ; +NET "ser_r<3>" LOC = "W21" ; +NET "ser_r<2>" LOC = "AC23" ; +NET "ser_r<1>" LOC = "AC24" ; +NET "ser_r<0>" LOC = "AE26" ; +NET "ser_rkmsb" LOC = "AD25" ; +NET "ser_rklsb" LOC = "Y20" ; + +## SRAM +NET "RAM_D<35>" LOC = "K16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<34>" LOC = "D20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<33>" LOC = "C20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<32>" LOC = "E21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<31>" LOC = "D21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<30>" LOC = "C21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<29>" LOC = "B21" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<28>" LOC = "H17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<27>" LOC = "G17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<26>" LOC = "B23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<25>" LOC = "A22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<24>" LOC = "D23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<23>" LOC = "C23" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<22>" LOC = "D22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<21>" LOC = "C22" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<20>" LOC = "F19" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<19>" LOC = "G20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<18>" LOC = "F20" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<17>" LOC = "F7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<16>" LOC = "E7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<15>" LOC = "G9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<14>" LOC = "H9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<13>" LOC = "G10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<12>" LOC = "H10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<11>" LOC = "A4" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<10>" LOC = "B4" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<9>" LOC = "C5" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<8>" LOC = "D6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<7>" LOC = "J11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<6>" LOC = "K11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<5>" LOC = "B7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<4>" LOC = "C7" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<3>" LOC = "B6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<2>" LOC = "C6" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<1>" LOC = "C8" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_D<0>" LOC = "D8" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<0>" LOC = "C11" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<1>" LOC = "E12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<2>" LOC = "F12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<3>" LOC = "D13" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<4>" LOC = "C12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<5>" LOC = "A12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<6>" LOC = "B12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<7>" LOC = "E14" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<8>" LOC = "F14" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<9>" LOC = "B15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<10>" LOC = "A15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<11>" LOC = "D16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<12>" LOC = "C15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<13>" LOC = "D17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<14>" LOC = "C16" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<15>" LOC = "F15" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<16>" LOC = "C17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<17>" LOC = "B17" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<18>" LOC = "B18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<19>" LOC = "A18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_A<20>" LOC = "D18" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<3>" LOC = "D9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<2>" LOC = "A9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<1>" LOC = "B9" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_BWn<0>" LOC = "G12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_ZZ" LOC = "J12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_LDn" LOC = "H12" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_OEn" LOC = "C10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_WEn" LOC = "D10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_CENn" LOC = "B10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; +NET "RAM_CLK" LOC = "A10" |IOSTANDARD = LVCMOS25 |DRIVE = 8 |SLEW = FAST ; + +## SPI Flash +NET "flash_miso" LOC = "AF24" ; +NET "flash_clk" LOC = "AE24" ; +NET "flash_mosi" LOC = "AB15" ; +NET "flash_cs" LOC = "AA7" ; + +## MISC FPGA, unused for now +#NET "PROG_B" LOC = "A2" ; +#NET "PUDC_B" LOC = "G8" ; +#NET "DONE" LOC = "AB21" ; +#NET "INIT_B" LOC = "AA15" ; + + +#NET "unnamed_net19" LOC = "AE9" ; # VS1 +#NET "unnamed_net18" LOC = "AF9" ; # VS0 +#NET "unnamed_net17" LOC = "AA12" ; # VS2 +#NET "unnamed_net16" LOC = "Y7" ; # M2 +#NET "unnamed_net15" LOC = "AC4" ; # M1 +#NET "unnamed_net14" LOC = "AD4" ; # M0 +#NET "unnamed_net13" LOC = "D4" ; # TMS +#NET "unnamed_net12" LOC = "E23" ; # TDO +#NET "unnamed_net11" LOC = "G7" ; # TDI +#NET "unnamed_net10" LOC = "A25" ; # TCK +#NET "unnamed_net20" LOC = "V20" ; # SUSPEND + + +NET "clk_to_mac" TNM_NET = "clk_to_mac"; +TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; + +NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; + +NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; +TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; + +NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; +TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; + +TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns; + +#NET "CLK_FPGA_P" CLOCK_DEDICATED_ROUTE = FALSE; +#PIN "DCM_INST/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; + +#NET "RAM_CLK" CLOCK_DEDICATED_ROUTE = FALSE; +#PIN "DCM_INST1/DCM_SP.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE; + + diff --git a/fpga/usrp2/top/N2x0/u2plus.v b/fpga/usrp2/top/N2x0/u2plus.v new file mode 100644 index 000000000..be1f355d2 --- /dev/null +++ b/fpga/usrp2/top/N2x0/u2plus.v @@ -0,0 +1,473 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +`timescale 1ns / 1ps +//`define LVDS 1 +//`define DCM_FOR_RAMCLK +////////////////////////////////////////////////////////////////////////////////// + +module u2plus + ( + input CLK_FPGA_P, input CLK_FPGA_N, // Diff + + // ADC + input ADC_clkout_p, input ADC_clkout_n, + input ADCA_12_p, input ADCA_12_n, + input ADCA_10_p, input ADCA_10_n, + input ADCA_8_p, input ADCA_8_n, + input ADCA_6_p, input ADCA_6_n, + input ADCA_4_p, input ADCA_4_n, + input ADCA_2_p, input ADCA_2_n, + input ADCA_0_p, input ADCA_0_n, + input ADCB_12_p, input ADCB_12_n, + input ADCB_10_p, input ADCB_10_n, + input ADCB_8_p, input ADCB_8_n, + input ADCB_6_p, input ADCB_6_n, + input ADCB_4_p, input ADCB_4_n, + input ADCB_2_p, input ADCB_2_n, + input ADCB_0_p, input ADCB_0_n, + + // DAC + output reg [15:0] DACA, + output reg [15:0] DACB, + input DAC_LOCK, // unused for now + + // DB IO Pins + inout [15:0] io_tx, + inout [15:0] io_rx, + + // Misc, debug + output [5:1] leds, // LED4 is shared w/INIT_B + input FPGA_RESET, + output [1:0] debug_clk, + output [31:0] debug, + output [3:1] TXD, input [3:1] RXD, // UARTs + //input [3:0] dipsw, // Forgot DIP Switches... + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input CLK_FUNC, // FIXME is an input to control the 9510 + input clk_status, + + inout SCL, inout SDA, // I2C + + // PPS + input PPS_IN, input PPS2_IN, + + // SPI + output SEN_CLK, output SCLK_CLK, output MOSI_CLK, input MISO_CLK, + output SEN_DAC, output SCLK_DAC, output MOSI_DAC, input MISO_DAC, + output SEN_ADC, output SCLK_ADC, output MOSI_ADC, + output SEN_TX_DB, output SCLK_TX_DB, output MOSI_TX_DB, input MISO_TX_DB, + output SEN_TX_DAC, output SCLK_TX_DAC, output MOSI_TX_DAC, + output SEN_TX_ADC, output SCLK_TX_ADC, output MOSI_TX_ADC, input MISO_TX_ADC, + output SEN_RX_DB, output SCLK_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, + output SEN_RX_DAC, output SCLK_RX_DAC, output MOSI_RX_DAC, + output SEN_RX_ADC, output SCLK_RX_ADC, output MOSI_RX_ADC, input MISO_RX_ADC, + + // GigE PHY + input CLK_TO_MAC, + + output reg [7:0] GMII_TXD, + output reg GMII_TX_EN, + output reg GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + input GMII_RX_CLK, + input [7:0] GMII_RXD, + input GMII_RX_DV, + input GMII_RX_ER, + input GMII_COL, + input GMII_CRS, + + input PHY_INTn, // open drain + inout MDIO, + output MDC, + output PHY_RESETn, + output ETH_LED, + +// input POR, + + // Expansion + input exp_time_in_p, input exp_time_in_n, // Diff + output exp_time_out_p, output exp_time_out_n, // Diff + input exp_user_in_p, input exp_user_in_n, // Diff + output exp_user_out_p, output exp_user_out_n, // Diff + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output reg [15:0] ser_t, + output reg ser_tklsb, + output reg ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // SRAM + inout [35:0] RAM_D, + output [20:0] RAM_A, + output [3:0] RAM_BWn, + output RAM_ZZ, + output RAM_LDn, + output RAM_OEn, + output RAM_WEn, + output RAM_CENn, + output RAM_CLK, + + // SPI Flash + output flash_cs, + output flash_clk, + output flash_mosi, + input flash_miso + ); + + wire CLK_TO_MAC_int, CLK_TO_MAC_int2; + IBUFG phyclk (.O(CLK_TO_MAC_int), .I(CLK_TO_MAC)); + BUFG phyclk2 (.O(CLK_TO_MAC_int2), .I(CLK_TO_MAC_int)); + + // FPGA-specific pins connections + wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + wire exp_time_in; + IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); + defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_time_out; + OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); + defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; + + wire exp_user_in; + IBUFDS exp_user_in_pin (.O(exp_user_in),.I(exp_user_in_p),.IB(exp_user_in_n)); + defparam exp_user_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_user_out; + OBUFDS exp_user_out_pin (.O(exp_user_out_p),.OB(exp_user_out_n),.I(exp_user_out)); + defparam exp_user_out_pin.IOSTANDARD = "LVDS_25"; + + reg [5:0] clock_ready_d; + always @(posedge clk_fpga) + clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; + wire dcm_rst = ~&clock_ready_d & |clock_ready_d; + + // ADC A is inverted on the schematic to facilitate a clean layout + // We account for that here by inverting it +`ifdef LVDS + wire [13:0] adc_a, adc_a_inv, adc_b; + capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds + (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), + .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p}, + {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), + .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n}, + {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), + .out({adc_a_inv,adc_b})); + assign adc_a = ~adc_a_inv; +`else + reg [13:0] adc_a, adc_b, adc_a_pre, adc_b_pre; + always @(posedge dsp_clk) + begin + adc_a_pre <= {ADCA_12_p,ADCA_12_n, ADCA_10_p,ADCA_10_n, ADCA_8_p,ADCA_8_n, ADCA_6_p,ADCA_6_n, + ADCA_4_p,ADCA_4_n, ADCA_2_p,ADCA_2_n, ADCA_0_p,ADCA_0_n }; + adc_b_pre <= {ADCB_12_p,ADCB_12_n, ADCB_10_p,ADCB_10_n, ADCB_8_p,ADCB_8_n, ADCB_6_p,ADCB_6_n, + ADCB_4_p,ADCB_4_n, ADCB_2_p,ADCB_2_n, ADCB_0_p,ADCB_0_n }; + adc_a <= ~adc_a_pre; //Note: A must be inverted, but not B + adc_b <= adc_b_pre; + end +`endif // !`ifdef LVDS + + // Handle Clocks + DCM DCM_INST (.CLKFB(dsp_clk), + .CLKIN(clk_fpga), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(), + .CLK180(), + .CLK270(clk270_100), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 10.000; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + // Create clock for external SRAM thats -90degree phase to DSPCLK (i.e) 2nS earlier at 100MHz. + BUFG clk270_100_buf_i1 (.I(clk270_100), + .O(clk270_100_buf)); + OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK), + .C0(clk270_100_buf), + .C1(~clk270_100_buf), + .CE(1'b1), + .D0(1'b1), + .D1(1'b0), + .R(1'b0), + .S(1'b0)); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // LEDs are active low outputs + wire [5:0] leds_int; + assign {ETH_LED,leds} = {6'b011111 ^ leds_int}; // drive low to turn on leds + + // SPI + wire miso, mosi, sclk; + + assign {SCLK_CLK,MOSI_CLK} = ~SEN_CLK ? {sclk,mosi} : 2'B0; + assign {SCLK_DAC,MOSI_DAC} = ~SEN_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_ADC,MOSI_ADC} = ~SEN_ADC ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_DAC,MOSI_TX_DAC} = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_ADC,MOSI_TX_ADC} = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_DAC,MOSI_RX_DAC} = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_ADC,MOSI_RX_ADC} = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0; + + assign miso = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) | + (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) | + (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC); + + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; + wire [7:0] GMII_TXD_unreg; + wire GMII_GTX_CLK_int; + + always @(posedge GMII_GTX_CLK_int) + begin + GMII_TX_EN <= GMII_TX_EN_unreg; + GMII_TX_ER <= GMII_TX_ER_unreg; + GMII_TXD <= GMII_TXD_unreg; + end + + OFDDRRSE OFDDRRSE_gmii_inst + (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) + .C0(GMII_GTX_CLK_int), // 0 degree clock input + .C1(~GMII_GTX_CLK_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + + wire ser_tklsb_unreg, ser_tkmsb_unreg; + wire [15:0] ser_t_unreg; + wire ser_tx_clk_int; + + always @(posedge ser_tx_clk_int) + begin + ser_tklsb <= ser_tklsb_unreg; + ser_tkmsb <= ser_tkmsb_unreg; + ser_t <= ser_t_unreg; + end + + assign ser_tx_clk = clk_fpga; + + reg [15:0] ser_r_int; + reg ser_rklsb_int, ser_rkmsb_int; + + always @(posedge ser_rx_clk) + begin + ser_r_int <= ser_r; + ser_rklsb_int <= ser_rklsb; + ser_rkmsb_int <= ser_rkmsb; + end + + /* + OFDDRRSE OFDDRRSE_serdes_inst + (.Q(ser_tx_clk), // Data output (connect directly to top-level port) + .C0(ser_tx_clk_int), // 0 degree clock input + .C1(~ser_tx_clk_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + */ + + + // + // Instantiate IO for Bidirectional bus to SRAM + // + wire [35:0] RAM_D_pi; + wire [35:0] RAM_D_po; + wire RAM_D_poe; + + genvar i; + + generate + for (i=0;i<36;i=i+1) + begin : gen_RAM_D_IO + + IOBUF #( + .DRIVE(12), + .IOSTANDARD("LVCMOS25"), + .SLEW("FAST") + ) + RAM_D_i ( + .O(RAM_D_pi[i]), + .I(RAM_D_po[i]), + .IO(RAM_D[i]), + .T(RAM_D_poe) + ); + end // block: gen_RAM_D_IO + endgenerate + + + + wire [15:0] dac_a_int, dac_b_int; + // DAC A and B are swapped in schematic to facilitate clean layout + // DAC A is also inverted in schematic to facilitate clean layout + always @(negedge dsp_clk) DACA <= ~dac_b_int; + always @(negedge dsp_clk) DACB <= dac_a_int; + + wire pps; + assign pps = PPS_IN ^ PPS2_IN; + + u2plus_core u2p_c(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (CLK_TO_MAC_int2), + .pps_in (pps), + .leds (leds_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_time_in (exp_time_in), + .exp_time_out (exp_time_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .adc_a (adc_a[13:0]), + .adc_ovf_a (1'b0), + .adc_on_a (), + .adc_oe_a (), + .adc_b (adc_b[13:0]), + .adc_ovf_b (1'b0), + .adc_on_b (), + .adc_oe_b (), + .dac_a (dac_a_int[15:0]), + .dac_b (dac_b_int[15:0]), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk), + .mosi (mosi), + .miso (miso), + .sen_clk (SEN_CLK), + .sen_dac (SEN_DAC), + .sen_adc (SEN_ADC), + .sen_tx_db (SEN_TX_DB), + .sen_tx_adc (SEN_TX_ADC), + .sen_tx_dac (SEN_TX_DAC), + .sen_rx_db (SEN_RX_DB), + .sen_rx_adc (SEN_RX_ADC), + .sen_rx_dac (SEN_RX_DAC), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D_po (RAM_D_po), + .RAM_D_pi (RAM_D_pi), + .RAM_D_poe (RAM_D_poe), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (TXD[3:1]), + .uart_rx_i ({1'b1,RXD[3:1]}), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2), + .button (FPGA_RESET), + .spiflash_cs (flash_cs), + .spiflash_clk (flash_clk), + .spiflash_miso (flash_miso), + .spiflash_mosi (flash_mosi) + ); + + // Drive low so that RAM does not sleep. + assign RAM_ZZ = 0; + // Byte Writes are qualified by the global write enable + // Always do 36bit operations to extram. + assign RAM_BWn = 4'b0000; + +endmodule // u2plus diff --git a/fpga/usrp2/top/N2x0/u2plus_core.v b/fpga/usrp2/top/N2x0/u2plus_core.v new file mode 100644 index 000000000..e2539e183 --- /dev/null +++ b/fpga/usrp2/top/N2x0/u2plus_core.v @@ -0,0 +1,772 @@ +// +// Copyright 2011-2012 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +// //////////////////////////////////////////////////////////////////////////////// +// Module Name: u2_core +// //////////////////////////////////////////////////////////////////////////////// + +module u2plus_core + (// Clocks + input dsp_clk, + input wb_clk, + output clock_ready, + input clk_to_mac, + input pps_in, + + // Misc, debug + output [7:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + + // Expansion + input exp_time_in, + output exp_time_out, + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output [7:0] GMII_TXD, + output GMII_TX_EN, + output GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output [15:0] ser_t, + output ser_tklsb, + output ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + input por, + output config_success, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_on_a, + output adc_oe_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_on_b, + output adc_oe_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + + // I2C + input scl_pad_i, + output scl_pad_o, + output scl_pad_oen_o, + input sda_pad_i, + output sda_pad_o, + output sda_pad_oen_o, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Generic SPI + output sclk, + output mosi, + input miso, + output sen_clk, + output sen_dac, + output sen_adc, + output sen_tx_db, + output sen_tx_adc, + output sen_tx_dac, + output sen_rx_db, + output sen_rx_adc, + output sen_rx_dac, + + // GPIO to DBoards + inout [15:0] io_tx, + inout [15:0] io_rx, + + // External RAM + input [35:0] RAM_D_pi, + output [35:0] RAM_D_po, + output RAM_D_poe, + output [20:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // Debug stuff + output [3:0] uart_tx_o, + input [3:0] uart_rx_i, + output [3:0] uart_baud_o, + input sim_mode, + input [3:0] clock_divider, + input button, + + output spiflash_cs, output spiflash_clk, input spiflash_miso, output spiflash_mosi + ); + + localparam SR_MISC = 0; // 7 regs + localparam SR_USER_REGS = 8; // 2 + localparam SR_TIME64 = 10; // 6 + localparam SR_BUF_POOL = 16; // 4 + localparam SR_SPI_CORE = 20; // 3 + localparam SR_RX_FRONT = 24; // 5 + localparam SR_RX_CTRL0 = 32; // 9 + localparam SR_RX_DSP0 = 48; // 7 + localparam SR_RX_CTRL1 = 80; // 9 + localparam SR_RX_DSP1 = 96; // 7 + + localparam SR_TX_FRONT = 128; // ? + localparam SR_TX_CTRL = 144; // 6 + localparam SR_TX_DSP = 160; // 5 + + localparam SR_GPIO = 184; // 5 + localparam SR_UDP_SM = 192; // 64 + + // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 + // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs + // localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo + localparam DSP_RX_FIFOSIZE = 10; + localparam DSP_TX_FIFOSIZE = 10; + localparam ETH_TX_FIFOSIZE = 9; + localparam ETH_RX_FIFOSIZE = 11; + localparam SERDES_TX_FIFOSIZE = 9; + localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? + + wire [7:0] set_addr, set_addr_dsp, set_addr_user; + wire [31:0] set_data, set_data_dsp, set_data_user; + wire set_stb, set_stb_dsp, set_stb_user; + + reg wb_rst; + wire dsp_rst = wb_rst; + + wire [31:0] status; + wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; + wire proc_int, overrun0, overrun1, underrun; + wire [3:0] uart_tx_int, uart_rx_int; + + wire [31:0] debug_gpio_0, debug_gpio_1; + + wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2; + + wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; + wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; + wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; + + wire serdes_link_up, good_sync; + wire epoch; + wire [31:0] irq; + wire [63:0] vita_time, vita_time_pps; + + wire run_rx0, run_rx1, run_tx; + reg run_rx0_d1, run_rx1_d1; + + // /////////////////////////////////////////////////////////////////////////////////////////////// + // Wishbone Single Master INTERCON + localparam dw = 32; // Data bus width + localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space + localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. + + wire [dw-1:0] m0_dat_o, m0_dat_i; + wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, + s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, + s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, + sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o, sf_dat_i, sf_dat_o; + wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; + wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; + wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; + wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; + wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; + wire m0_err, m0_rty; + wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we; + + wb_1master #(.decode_w(8), + .s0_addr(8'b0000_0000),.s0_mask(8'b1100_0000), // Main RAM (0-16K) + .s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000), // Packet Router (16-20K) + .s2_addr(8'b0101_0000),.s2_mask(8'b1111_1100), // SPI + .s3_addr(8'b0101_0100),.s3_mask(8'b1111_1100), // I2C + .s4_addr(8'b0101_1000),.s4_mask(8'b1111_1100), // Unused + .s5_addr(8'b0101_1100),.s5_mask(8'b1111_1100), // Readback + .s6_addr(8'b0110_0000),.s6_mask(8'b1111_0000), // Ethernet MAC + .s7_addr(8'b0111_0000),.s7_mask(8'b1111_0000), // Settings Bus (only uses 1K) + .s8_addr(8'b1000_0000),.s8_mask(8'b1111_1100), // PIC + .s9_addr(8'b1000_0100),.s9_mask(8'b1111_1100), // Unused + .sa_addr(8'b1000_1000),.sa_mask(8'b1111_1100), // UART + .sb_addr(8'b1000_1100),.sb_mask(8'b1111_1100), // Unused + .sc_addr(8'b1001_0000),.sc_mask(8'b1111_0000), // Unused + .sd_addr(8'b1010_0000),.sd_mask(8'b1111_0000), // ICAP + .se_addr(8'b1011_0000),.se_mask(8'b1111_0000), // SPI Flash + .sf_addr(8'b1100_0000),.sf_mask(8'b1100_0000), // 48K-64K, Boot RAM + .dw(dw),.aw(aw),.sw(sw)) wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), + .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0)); + + assign s2_ack = 0; + assign s4_ack = 0; + assign s9_ack = 0; + assign sb_ack = 0; + assign sc_ack = 0; + + // //////////////////////////////////////////////////////////////////////////////////////// + // Reset Controller + + reg cpu_bldr_ctrl_state; + localparam CPU_BLDR_CTRL_WAIT = 0; + localparam CPU_BLDR_CTRL_DONE = 1; + + wire bldr_done; + wire por_rst; + wire [aw-1:0] cpu_adr; + + // Swap boot ram and main ram when in bootloader mode + assign m0_adr = (^cpu_adr[15:14] | (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_DONE)) ? cpu_adr : + cpu_adr ^ 16'hC000; + + system_control sysctrl + (.wb_clk_i(wb_clk), .wb_rst_o(por_rst), .ram_loader_done_i(1'b1) ); + + always @(posedge wb_clk) + if(por_rst) begin + cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_WAIT; + wb_rst <= 1'b1; + end + else begin + case(cpu_bldr_ctrl_state) + + CPU_BLDR_CTRL_WAIT: begin + wb_rst <= 1'b0; + if (bldr_done == 1'b1) begin //set by the bootloader + cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_DONE; + wb_rst <= 1'b1; + end + end + + CPU_BLDR_CTRL_DONE: begin //stay here forever + wb_rst <= 1'b0; + end + + endcase //cpu_bldr_ctrl_state + end + + // ///////////////////////////////////////////////////////////////////////// + // Processor + + assign bus_error = m0_err | m0_rty; + + wire [63:0] zpu_status; + zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) + zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(~wb_rst), + // Data Wishbone bus to system bus fabric + .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(cpu_adr), + .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), + // Interrupts and exceptions + .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); + + // ///////////////////////////////////////////////////////////////////////// + // Dual Ported Boot RAM -- D-Port is Slave #0 on main Wishbone + // Dual Ported Main RAM -- D-Port is Slave #F on main Wishbone + // I-port connects directly to processor + + bootram bootram(.clk(wb_clk), .reset(wb_rst), + .if_adr(14'b0), .if_data(), + .dwb_adr_i(sf_adr[13:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i), + .dwb_we_i(sf_we), .dwb_ack_o(sf_ack), .dwb_stb_i(sf_stb), .dwb_sel_i(sf_sel)); + +////blinkenlights v0.1 +//defparam bootram.RAM0.INIT_00=256'hbc32fff0_aa43502b_b00000fe_30630001_80000000_10600000_a48500ff_10a00000; +//defparam bootram.RAM0.INIT_01=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_308000ff_be23000c_a4640001; + +`include "bootloader.rmi" + + ram_harvard2 #(.AWIDTH(14),.RAM_SIZE(16384)) + sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .if_adr(14'b0), .if_data(), + .dwb_adr_i(s0_adr[13:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool, slave #1 + wire rd0_ready_i, rd0_ready_o; + wire rd1_ready_i, rd1_ready_o; + wire rd2_ready_i, rd2_ready_o; + wire rd3_ready_i, rd3_ready_o; + wire [35:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + + wire wr0_ready_i, wr0_ready_o; + wire wr1_ready_i, wr1_ready_o; + wire wr2_ready_i, wr2_ready_o; + wire wr3_ready_i, wr3_ready_o; + wire [35:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + + wire [35:0] sfc_wr_data, sfc_rd_data; + wire sfc_wr_ready, sfc_rd_ready; + wire sfc_wr_valid, sfc_rd_valid; + + wire [35:0] tx_err_data; + wire tx_err_src_rdy, tx_err_dst_rdy; + + wire [31:0] router_debug; + + packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), + + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0), + + .status(status), .sys_int_o(buffer_int), .debug(router_debug), + + .ser_inp_data(wr0_dat), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), + .dsp0_inp_data(wr1_dat), .dsp0_inp_valid(wr1_ready_i), .dsp0_inp_ready(wr1_ready_o), + .dsp1_inp_data(wr3_dat), .dsp1_inp_valid(wr3_ready_i), .dsp1_inp_ready(wr3_ready_o), + .eth_inp_data(wr2_dat), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), + .err_inp_data(tx_err_data), .err_inp_valid(tx_err_src_rdy), .err_inp_ready(tx_err_dst_rdy), + .ctl_inp_data(sfc_wr_data), .ctl_inp_valid(sfc_wr_valid), .ctl_inp_ready(sfc_wr_ready), + + .ser_out_data(rd0_dat), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), + .dsp_out_data(rd1_dat), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), + .ctl_out_data(sfc_rd_data), .ctl_out_valid(sfc_rd_valid), .ctl_out_ready(sfc_rd_ready), + .eth_out_data(rd2_dat), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) + ); + + // ///////////////////////////////////////////////////////////////////////// + // SPI -- Slave #2 + wire [31:0] spi_debug; + wire [31:0] spi_readback; + wire spi_ready; + simple_spi_core #(.BASE(SR_SPI_CORE), .WIDTH(9)) shared_spi( + .clock(dsp_clk), .reset(dsp_rst), + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .readback(spi_readback), .ready(spi_ready), + .sen({sen_adc, sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .sclk(sclk), .mosi(mosi), .miso(miso), .debug(spi_debug) + ); + + // ///////////////////////////////////////////////////////////////////////// + // I2C -- Slave #3 + i2c_master_top #(.ARST_LVL(1)) + i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_i[31:8] = 24'd0; + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs + + wire [31:0] gpio_readback; + + gpio_atr #(.BASE(SR_GPIO), .WIDTH(32)) + gpio_atr(.clk(dsp_clk),.reset(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .rx(run_rx0_d1 | run_rx1_d1), .tx(run_tx), + .gpio({io_tx,io_rx}), .gpio_readback(gpio_readback) ); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool Status -- Slave #5 + + //compatibility number -> increment when the fpga has been sufficiently altered + localparam compat_num = {16'd10, 16'd0}; //major, minor + + wire [31:0] irq_readback = {18'b0, button, spi_ready, clk_status, serdes_link_up, 10'b0}; + + wb_readback_mux buff_pool_status + (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), + .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), + + .word00(spi_readback),.word01(32'hffff_ffff),.word02(32'hffff_ffff),.word03(32'hffff_ffff), + .word04(32'hffff_ffff),.word05(32'hffff_ffff),.word06(32'hffff_ffff),.word07(32'hffff_ffff), + .word08(status),.word09(32'hffff_ffff),.word10(32'hffff_ffff), + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq_readback), + .word14(32'hffff_ffff),.word15(32'hffff_ffff) + ); + + // ///////////////////////////////////////////////////////////////////////// + // Ethernet MAC Slave #6 + + simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE), + .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper + (.clk125(clk_to_mac), .reset(wb_rst), + .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), + .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), + .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), + .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), + .sys_clk(dsp_clk), + .rx_f36_data(wr2_dat), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), + .tx_f36_data(rd2_dat), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), + .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), + .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), + .mdio(MDIO), .mdc(MDC), + .debug(debug_mac)); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #7 + settings_bus settings_bus + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), + .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), + .strobe(set_stb),.addr(set_addr),.data(set_data)); + + assign s7_dat_i = 32'd0; + + wire set_stb_dsp0, set_stb_dsp1; + wire [31:0] set_data_dsp0, set_data_dsp1; + wire [7:0] set_addr_dsp0, set_addr_dsp1; + + //mux settings_bus_crossclock and settings_readback_bus_fifo_ctrl with prio + assign set_stb_dsp = set_stb_dsp0 | set_stb_dsp1; + assign set_addr_dsp = set_stb_dsp1? set_addr_dsp1 : set_addr_dsp0; + assign set_data_dsp = set_stb_dsp1? set_data_dsp1 : set_data_dsp0; + + settings_bus_crossclock #(.FLOW_CTRL(1/*on*/)) settings_bus_crossclock + (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), + .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp0), .set_addr_o(set_addr_dsp0), .set_data_o(set_data_dsp0), + .blocked(set_stb_dsp1)); + + user_settings #(.BASE(SR_USER_REGS)) user_settings + (.clk(dsp_clk),.rst(dsp_rst),.set_stb(set_stb_dsp), + .set_addr(set_addr_dsp),.set_data(set_data_dsp), + .set_addr_user(set_addr_user),.set_data_user(set_data_user), + .set_stb_user(set_stb_user) ); + + // ///////////////////////////////////////////////////////////////////////// + // Settings + Readback Bus -- FIFO controlled + + wire [31:0] sfc_debug; + wire sfc_clear; + settings_fifo_ctrl #(.PROT_DEST(3), .PROT_HDR(1)) sfc + ( + .clock(dsp_clk), .reset(dsp_rst), .clear(sfc_clear), + .vita_time(vita_time), .perfs_ready(spi_ready), + .in_data(sfc_rd_data), .in_valid(sfc_rd_valid), .in_ready(sfc_rd_ready), + .out_data(sfc_wr_data), .out_valid(sfc_wr_valid), .out_ready(sfc_wr_ready), + .strobe(set_stb_dsp1), .addr(set_addr_dsp1), .data(set_data_dsp1), + .word00(spi_readback),.word01(32'hffff_ffff),.word02(32'hffff_ffff),.word03(32'hffff_ffff), + .word04(32'hffff_ffff),.word05(32'hffff_ffff),.word06(32'hffff_ffff),.word07(32'hffff_ffff), + .word08(32'hffff_ffff),.word09(gpio_readback),.word10(vita_time[63:32]), + .word11(vita_time[31:0]),.word12(32'hffff_ffff),.word13(irq_readback), + .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]), + .debug(sfc_debug) + ); + + setting_reg #(.my_addr(SR_BUF_POOL+1/*same as packet dispatcher*/),.width(1)) sr_clear_sfc + (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.changed(sfc_clear)); + + // Output control lines + wire [7:0] clock_outs, serdes_outs, adc_outs; + assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; + assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; + assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; + + wire phy_reset; + assign PHY_RESETn = ~phy_reset; + + setting_reg #(.my_addr(SR_MISC+0),.width(8)) sr_clk + (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),.in(set_data),.out(clock_outs),.changed()); + + setting_reg #(.my_addr(SR_MISC+1),.width(8)) sr_ser + (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.out(serdes_outs),.changed()); + + setting_reg #(.my_addr(SR_MISC+2),.width(8)) sr_adc + (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.out(adc_outs),.changed()); + + setting_reg #(.my_addr(SR_MISC+4),.width(1)) sr_phy + (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.out(phy_reset),.changed()); + + setting_reg #(.my_addr(SR_MISC+5),.width(1)) sr_bld + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),.in(set_data),.out(bldr_done),.changed()); + + // ///////////////////////////////////////////////////////////////////////// + // LEDS + // register 8 determines whether leds are controlled by SW or not + // 1 = controlled by HW, 0 = by SW + // In Rev3 there are only 6 leds, and the highest one is on the ETH connector + + wire [7:0] led_src, led_sw; + wire [7:0] led_hw = {run_tx, (run_rx0_d1 | run_rx1_d1), clk_status, serdes_link_up & good_sync, 1'b0}; + + setting_reg #(.my_addr(SR_MISC+3),.width(8)) sr_led + (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.out(led_sw),.changed()); + + setting_reg #(.my_addr(SR_MISC+6),.width(8), .at_reset(8'b0001_1110)) sr_led_src + (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp), .in(set_data_dsp),.out(led_src),.changed()); + + assign leds = (led_src & led_hw) | (~led_src & led_sw); + + // ///////////////////////////////////////////////////////////////////////// + // Interrupt Controller, Slave #8 + + assign irq= {{8'b0}, + {uart_tx_int[3:0], uart_rx_int[3:0]}, + {4'b0, clk_status, 3'b0}, + {3'b0, PHY_INTn,i2c_int,spi_int,2'b00}}; + + pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), + .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), + .irq(irq) ); + + // ///////////////////////////////////////////////////////////////////////// + // UART, Slave #10 + + quad_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), + .adr_i(sa_adr[6:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), + .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), + .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); + // ///////////////////////////////////////////////////////////////////////// + // ICAP for reprogramming the FPGA, Slave #13 (D) + + s3a_icap_wb s3a_icap_wb + (.clk(wb_clk), .reset(wb_rst), .cyc_i(sd_cyc), .stb_i(sd_stb), + .we_i(sd_we), .ack_o(sd_ack), .dat_i(sd_dat_o), .dat_o(sd_dat_i)); + + // ///////////////////////////////////////////////////////////////////////// + // SPI for Flash -- Slave #14 (E) + spi_top flash_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(se_adr[4:0]),.wb_dat_i(se_dat_o), + .wb_dat_o(se_dat_i),.wb_sel_i(se_sel),.wb_we_i(se_we),.wb_stb_i(se_stb), + .wb_cyc_i(se_cyc),.wb_ack_o(se_ack),.wb_err_o(se_err),.wb_int_o(spiflash_int), + .ss_pad_o(spiflash_cs), + .sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // ADC Frontend + wire [23:0] rx_fe_i, rx_fe_q; + + rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .adc_a({adc_a,2'b00}),.adc_ovf_a(adc_ovf_a), + .adc_b({adc_b,2'b00}),.adc_ovf_b(adc_ovf_b), + .i_out(rx_fe_i), .q_out(rx_fe_q), .run(run_rx0_d1 | run_rx1_d1), .debug()); + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX 0 + wire [31:0] sample_rx0; + wire strobe_rx0, clear_rx0; + + always @(posedge dsp_clk) + run_rx0_d1 <= run_rx0; + + ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0 + (.clk(dsp_clk), .rst(dsp_rst), .clr(clear_rx0), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), + .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q), + .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0), + .debug() ); + + vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE), .DSP_NUMBER(0)) vita_rx_chain0 + (.clk(dsp_clk), .reset(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), + .vita_time(vita_time), .overrun(overrun0), + .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), .clear_o(clear_rx0), + .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o), + .debug() ); + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX 1 + wire [31:0] sample_rx1; + wire strobe_rx1, clear_rx1; + + always @(posedge dsp_clk) + run_rx1_d1 <= run_rx1; + + ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1 + (.clk(dsp_clk), .rst(dsp_rst), .clr(clear_rx1), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), + .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q), + .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1), + .debug() ); + + vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE), .DSP_NUMBER(1)) vita_rx_chain1 + (.clk(dsp_clk), .reset(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), + .vita_time(vita_time), .overrun(overrun1), + .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), .clear_o(clear_rx1), + .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o), + .debug() ); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [35:0] tx_data; + wire tx_src_rdy, tx_dst_rdy; + wire [31:0] debug_vt; + wire clear_tx; + + assign RAM_A[20:18] = 3'b0; + + ext_fifo #(.EXT_WIDTH(36),.INT_WIDTH(36),.RAM_DEPTH(18),.FIFO_DEPTH(18)) + ext_fifo_i1 + (.int_clk(dsp_clk), + .ext_clk(dsp_clk), + .rst(dsp_rst | clear_tx), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A[17:0]), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .datain(rd1_dat), + .src_rdy_i(rd1_ready_o), + .dst_rdy_o(rd1_ready_i), + .dataout(tx_data), + .src_rdy_o(tx_src_rdy), + .dst_rdy_i(tx_dst_rdy), + .debug(debug_extfifo), + .debug2(debug_extfifo2) ); + + wire [23:0] tx_fe_i, tx_fe_q; + wire [31:0] sample_tx; + wire strobe_tx; + + vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(DSP_TX_FIFOSIZE), + .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), + .DSP_NUMBER(0)) + vita_tx_chain + (.clk(dsp_clk), .reset(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), + .sample(sample_tx), .strobe(strobe_tx), + .underrun(underrun), .run(run_tx), .clear_o(clear_tx), + .debug(debug_vt)); + + duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain + (.clk(dsp_clk),.rst(dsp_rst), .clr(clear_tx), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), + .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .debug() ); + + tx_frontend #(.BASE(SR_TX_FRONT)) tx_frontend + (.clk(dsp_clk), .rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(1'b1), + .dac_a(dac_a), .dac_b(dac_b)); + + // /////////////////////////////////////////////////////////////////////////////////// + // SERDES + + serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes + (.clk(dsp_clk),.rst(dsp_rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .rd_dat_i(rd0_dat[31:0]),.rd_flags_i(rd0_dat[35:32]),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .wr_dat_o(wr0_dat[31:0]),.wr_flags_o(wr0_dat[35:32]),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), + .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), + .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), + .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing + + wire [31:0] debug_sync; + + time_64bit #(.BASE(SR_TIME64)) time_64bit + (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), + .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), .good_sync(good_sync), .debug(debug_sync)); + + // ///////////////////////////////////////////////////////////////////////////////////////// + // Debug Pins + + assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; + assign debug = 32'd0; + assign debug_gpio_0 = 32'd0; + assign debug_gpio_1 = 32'd0; + +endmodule // u2_core diff --git a/fpga/usrp2/top/USRP2/.gitignore b/fpga/usrp2/top/USRP2/.gitignore new file mode 100644 index 000000000..f50a2b7e5 --- /dev/null +++ b/fpga/usrp2/top/USRP2/.gitignore @@ -0,0 +1,57 @@ +/*.ptwx +/*.xrpt +/*.zip +/*_xdb +/templates +/netgen +/_ngo +/_xmsgs +/_pace.ucf +/*.cmd +/*.ibs +/*.lfp +/*.mfp +/*.bit +/*.bin +/*.stx +/*.par +/*.unroutes +/*.ntrc_log +/*.ngr +/*.mrp +/*.html +/*.lso +/*.twr +/*.bld +/*.ncd +/*.txt +/*.cmd_log +/*.drc +/*.map +/*.twr +/*.xml +/*.syr +/*.ngm +/*.xst +/*.csv +/*.html +/*.lock +/*.ncd +/*.twx +/*.ise_ISE_Backup +/*.xml +/*.ut +/*.xpi +/*.ngd +/*.ncd +/*.pad +/*.bgn +/*.ngc +/*.pcf +/*.ngd +/xst +/*.log +/*.rpt +/*.cel +/*.restore +/build* diff --git a/fpga/usrp2/top/USRP2/Makefile b/fpga/usrp2/top/USRP2/Makefile new file mode 100644 index 000000000..94480a811 --- /dev/null +++ b/fpga/usrp2/top/USRP2/Makefile @@ -0,0 +1,104 @@ +# +# Copyright 2008-2012 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u2_rev3 +BUILD_DIR = $(abspath build) + +# set me in a custom makefile +CUSTOM_SRCS = +CUSTOM_DEFS = + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extramfifo/Makefile.srcs + + +################################################## +# Project Properties +################################################## +PROJECT_PROPERTIES = \ +family Spartan3 \ +device xc3s2000 \ +package fg456 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u2_core.v \ +u2_rev3.v \ +u2_rev3.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto \ +"Verilog Macros" "FIFO_CTRL_NO_TIME=1 $(CUSTOM_DEFS)" + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Generate Detailed MAP Report" TRUE \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/USRP2/u2_core.v b/fpga/usrp2/top/USRP2/u2_core.v new file mode 100644 index 000000000..d8fe8cf10 --- /dev/null +++ b/fpga/usrp2/top/USRP2/u2_core.v @@ -0,0 +1,771 @@ +// +// Copyright 2011-2012 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +// //////////////////////////////////////////////////////////////////////////////// +// Module Name: u2_core +// //////////////////////////////////////////////////////////////////////////////// + +module u2_core + (// Clocks + input dsp_clk, + input wb_clk, + output clock_ready, + input clk_to_mac, + input pps_in, + + // Misc, debug + output [7:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + + // Expansion + input exp_time_in, + output exp_time_out, + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output [7:0] GMII_TXD, + output GMII_TX_EN, + output GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output [15:0] ser_t, + output ser_tklsb, + output ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // CPLD interface + output cpld_start, + output cpld_mode, + output cpld_done, + input cpld_din, + input cpld_clk, + input cpld_detached, + output cpld_misc, + input cpld_init_b, + input por, + output config_success, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_on_a, + output adc_oe_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_on_b, + output adc_oe_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + + // I2C + input scl_pad_i, + output scl_pad_o, + output scl_pad_oen_o, + input sda_pad_i, + output sda_pad_o, + output sda_pad_oen_o, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Generic SPI + output sclk, + output mosi, + input miso, + output sen_clk, + output sen_dac, + output sen_tx_db, + output sen_tx_adc, + output sen_tx_dac, + output sen_rx_db, + output sen_rx_adc, + output sen_rx_dac, + + // GPIO to DBoards + inout [15:0] io_tx, + inout [15:0] io_rx, + + // External RAM + input [17:0] RAM_D_pi, + output [17:0] RAM_D_po, + output RAM_D_poe, + output [18:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // Debug stuff + output uart_tx_o, + input uart_rx_i, + output uart_baud_o, + input sim_mode, + input [3:0] clock_divider + ); + + localparam SR_MISC = 0; // 7 regs + localparam SR_USER_REGS = 8; // 2 + localparam SR_TIME64 = 10; // 6 + localparam SR_BUF_POOL = 16; // 4 + localparam SR_SPI_CORE = 20; // 3 + localparam SR_RX_FRONT = 24; // 5 + localparam SR_RX_CTRL0 = 32; // 9 + localparam SR_RX_DSP0 = 48; // 7 + localparam SR_RX_CTRL1 = 80; // 9 + localparam SR_RX_DSP1 = 96; // 7 + + localparam SR_TX_FRONT = 128; // ? + localparam SR_TX_CTRL = 144; // 6 + localparam SR_TX_DSP = 160; // 5 + + localparam SR_GPIO = 184; // 5 + localparam SR_UDP_SM = 192; // 64 + + // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 + // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs + // localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo + localparam DSP_RX_FIFOSIZE = 10; + localparam DSP_TX_FIFOSIZE = 10; + localparam ETH_TX_FIFOSIZE = 9; + localparam ETH_RX_FIFOSIZE = 11; + localparam SERDES_TX_FIFOSIZE = 9; + localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? + + wire [7:0] set_addr, set_addr_dsp, set_addr_user; + wire [31:0] set_data, set_data_dsp, set_data_user; + wire set_stb, set_stb_dsp, set_stb_user; + + wire ram_loader_done, ram_loader_rst; + wire wb_rst; + wire dsp_rst = wb_rst; + + wire [31:0] status; + wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; + wire proc_int, overrun0, overrun1, underrun; + wire uart_tx_int, uart_rx_int; + + wire [31:0] debug_gpio_0, debug_gpio_1; + + wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2; + + wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; + wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; + wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; + + wire serdes_link_up, good_sync; + wire epoch; + wire [31:0] irq; + wire [63:0] vita_time, vita_time_pps; + + wire run_rx0, run_rx1, run_tx; + reg run_rx0_d1, run_rx1_d1; + + // /////////////////////////////////////////////////////////////////////////////////////////////// + // Wishbone Single Master INTERCON + localparam dw = 32; // Data bus width + localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space + localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. + + wire [dw-1:0] m0_dat_o, m0_dat_i; + wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, + s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, + s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o, + sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o, sf_dat_i, sf_dat_o; + wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; + wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; + wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; + wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; + wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; + wire m0_err, m0_rty; + wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we; + + wb_1master #(.decode_w(8), + .s0_addr(8'b0000_0000),.s0_mask(8'b1100_0000), // Main RAM (0-16K) + .s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000), // Packet Router (16-20K) + .s2_addr(8'b0101_0000),.s2_mask(8'b1111_1100), // SPI + .s3_addr(8'b0101_0100),.s3_mask(8'b1111_1100), // I2C + .s4_addr(8'b0101_1000),.s4_mask(8'b1111_1100), // Unused + .s5_addr(8'b0101_1100),.s5_mask(8'b1111_1100), // Readback + .s6_addr(8'b0110_0000),.s6_mask(8'b1111_0000), // Ethernet MAC + .s7_addr(8'b0111_0000),.s7_mask(8'b1111_0000), // Settings Bus (only uses 1K) + .s8_addr(8'b1000_0000),.s8_mask(8'b1111_1100), // PIC + .s9_addr(8'b1000_0100),.s9_mask(8'b1111_1100), // Unused + .sa_addr(8'b1000_1000),.sa_mask(8'b1111_1100), // UART + .sb_addr(8'b1000_1100),.sb_mask(8'b1111_1100), // Unused + .sc_addr(8'b1001_0000),.sc_mask(8'b1111_0000), // Unused + .sd_addr(8'b1010_0000),.sd_mask(8'b1111_0000), // Unused + .se_addr(8'b1011_0000),.se_mask(8'b1111_0000), // Unused + .sf_addr(8'b1100_0000),.sf_mask(8'b1100_0000), // Unused + .dw(dw),.aw(aw),.sw(sw)) wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), + .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0)); + + assign s2_ack = 0; + assign s4_ack = 0; + assign s9_ack = 0; + assign sb_ack = 0; + assign sc_ack = 0; + assign sd_ack = 0; + assign se_ack = 0; + assign sf_ack = 0; + + // //////////////////////////////////////////////////////////////////////////////////////// + // Reset Controller + system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), + .ram_loader_rst_o(ram_loader_rst), + .wb_rst_o(wb_rst), + .ram_loader_done_i(ram_loader_done)); + + assign config_success = ram_loader_done; + reg takeover = 0; + + wire cpld_start_int, cpld_mode_int, cpld_done_int; + + always @(posedge wb_clk) + if(ram_loader_done) + takeover = 1; + assign cpld_misc = ~takeover; + + wire sd_clk, sd_csn, sd_mosi, sd_miso; + + assign sd_miso = cpld_din; + assign cpld_start = takeover ? sd_clk : cpld_start_int; + assign cpld_mode = takeover ? sd_csn : cpld_mode_int; + assign cpld_done = takeover ? sd_mosi : cpld_done_int; + + // /////////////////////////////////////////////////////////////////// + // RAM Loader + + wire [31:0] ram_loader_dat; + wire [15:0] ram_loader_adr; + wire [3:0] ram_loader_sel; + wire ram_loader_stb, ram_loader_we; + ram_loader #(.AWIDTH(aw),.RAM_SIZE(16384)) + ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst), + .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr), + .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel), + .wb_we(ram_loader_we), + .ram_loader_done(ram_loader_done), + // CPLD Interface + .cpld_clk(cpld_clk), + .cpld_din(cpld_din), + .cpld_start(cpld_start_int), + .cpld_mode(cpld_mode_int), + .cpld_done(cpld_done_int), + .cpld_detached(cpld_detached)); + + // ///////////////////////////////////////////////////////////////////////// + // Processor + + assign bus_error = m0_err | m0_rty; + + wire [63:0] zpu_status; + zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) + zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(ram_loader_done), + // Data Wishbone bus to system bus fabric + .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr), + .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), + // Interrupts and exceptions + .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); + + // ///////////////////////////////////////////////////////////////////////// + // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone + // I-port connects directly to processor and ram loader + + ram_harvard #(.AWIDTH(14),.RAM_SIZE(16384),.ICWIDTH(7),.DCWIDTH(6)) + sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + + .ram_loader_adr_i(ram_loader_adr[13:0]), .ram_loader_dat_i(ram_loader_dat), + .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), + .ram_loader_we_i(ram_loader_we), + .ram_loader_done_i(ram_loader_done), + + .if_adr(16'b0), .if_data(), + + .dwb_adr_i(s0_adr[13:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool, slave #1 + wire rd0_ready_i, rd0_ready_o; + wire rd1_ready_i, rd1_ready_o; + wire rd2_ready_i, rd2_ready_o; + wire rd3_ready_i, rd3_ready_o; + wire [35:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + + wire wr0_ready_i, wr0_ready_o; + wire wr1_ready_i, wr1_ready_o; + wire wr2_ready_i, wr2_ready_o; + wire wr3_ready_i, wr3_ready_o; + wire [35:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + + wire [35:0] sfc_wr_data, sfc_rd_data; + wire sfc_wr_ready, sfc_rd_ready; + wire sfc_wr_valid, sfc_rd_valid; + + wire [35:0] tx_err_data; + wire tx_err_src_rdy, tx_err_dst_rdy; + + wire [31:0] router_debug; + + packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), + + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0), + + .status(status), .sys_int_o(buffer_int), .debug(router_debug), + + .ser_inp_data(wr0_dat), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), + .dsp0_inp_data(wr1_dat), .dsp0_inp_valid(wr1_ready_i), .dsp0_inp_ready(wr1_ready_o), + .dsp1_inp_data(wr3_dat), .dsp1_inp_valid(wr3_ready_i), .dsp1_inp_ready(wr3_ready_o), + .eth_inp_data(wr2_dat), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), + .err_inp_data(tx_err_data), .err_inp_valid(tx_err_src_rdy), .err_inp_ready(tx_err_dst_rdy), + .ctl_inp_data(sfc_wr_data), .ctl_inp_valid(sfc_wr_valid), .ctl_inp_ready(sfc_wr_ready), + + .ser_out_data(rd0_dat), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), + .dsp_out_data(rd1_dat), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), + .ctl_out_data(sfc_rd_data), .ctl_out_valid(sfc_rd_valid), .ctl_out_ready(sfc_rd_ready), + .eth_out_data(rd2_dat), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) + ); + + // ///////////////////////////////////////////////////////////////////////// + // SPI -- Slave #2 + wire [31:0] spi_debug; + wire [31:0] spi_readback; + wire spi_ready; + simple_spi_core #(.BASE(SR_SPI_CORE), .WIDTH(8)) shared_spi( + .clock(dsp_clk), .reset(dsp_rst), + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .readback(spi_readback), .ready(spi_ready), + .sen({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .sclk(sclk), .mosi(mosi), .miso(miso), .debug(spi_debug) + ); + + // ///////////////////////////////////////////////////////////////////////// + // I2C -- Slave #3 + i2c_master_top #(.ARST_LVL(1)) + i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_i[31:8] = 24'd0; + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs + + wire [31:0] gpio_readback; + + gpio_atr #(.BASE(SR_GPIO), .WIDTH(32)) + gpio_atr(.clk(dsp_clk),.reset(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .rx(run_rx0_d1 | run_rx1_d1), .tx(run_tx), + .gpio({io_tx,io_rx}), .gpio_readback(gpio_readback) ); + + // ///////////////////////////////////////////////////////////////////////// + // Buffer Pool Status -- Slave #5 + + //compatibility number -> increment when the fpga has been sufficiently altered + localparam compat_num = {16'd10, 16'd0}; //major, minor + + wire [31:0] irq_readback = {19'b0, spi_ready, clk_status, serdes_link_up, 10'b0}; + + wb_readback_mux buff_pool_status + (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), + .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), + + .word00(spi_readback),.word01(32'hffff_ffff),.word02(32'hffff_ffff),.word03(32'hffff_ffff), + .word04(32'hffff_ffff),.word05(32'hffff_ffff),.word06(32'hffff_ffff),.word07(32'hffff_ffff), + .word08(status),.word09(gpio_readback),.word10(vita_time[63:32]), + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq_readback), + .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]) + ); + + // ///////////////////////////////////////////////////////////////////////// + // Ethernet MAC Slave #6 + + simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE), + .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper + (.clk125(clk_to_mac), .reset(wb_rst), + .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), + .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), + .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), + .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), + .sys_clk(dsp_clk), + .rx_f36_data(wr2_dat), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), + .tx_f36_data(rd2_dat), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), + .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), + .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), + .mdio(MDIO), .mdc(MDC), + .debug(debug_mac)); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #7 + settings_bus settings_bus + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), + .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), + .strobe(set_stb),.addr(set_addr),.data(set_data)); + + assign s7_dat_i = 32'd0; + + wire set_stb_dsp0, set_stb_dsp1; + wire [31:0] set_data_dsp0, set_data_dsp1; + wire [7:0] set_addr_dsp0, set_addr_dsp1; + + //mux settings_bus_crossclock and settings_readback_bus_fifo_ctrl with prio + assign set_stb_dsp = set_stb_dsp0 | set_stb_dsp1; + assign set_addr_dsp = set_stb_dsp1? set_addr_dsp1 : set_addr_dsp0; + assign set_data_dsp = set_stb_dsp1? set_data_dsp1 : set_data_dsp0; + + settings_bus_crossclock #(.FLOW_CTRL(1/*on*/)) settings_bus_crossclock + (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), + .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp0), .set_addr_o(set_addr_dsp0), .set_data_o(set_data_dsp0), + .blocked(set_stb_dsp1)); + + user_settings #(.BASE(SR_USER_REGS)) user_settings + (.clk(dsp_clk),.rst(dsp_rst),.set_stb(set_stb_dsp), + .set_addr(set_addr_dsp),.set_data(set_data_dsp), + .set_addr_user(set_addr_user),.set_data_user(set_data_user), + .set_stb_user(set_stb_user) ); + + // ///////////////////////////////////////////////////////////////////////// + // Settings + Readback Bus -- FIFO controlled + + wire [31:0] sfc_debug; + wire sfc_clear; + /* + settings_fifo_ctrl #(.PROT_DEST(3), .PROT_HDR(1)) sfc + ( + .clock(dsp_clk), .reset(dsp_rst), .clear(sfc_clear), + .vita_time(vita_time), .perfs_ready(spi_ready), + .in_data(sfc_rd_data), .in_valid(sfc_rd_valid), .in_ready(sfc_rd_ready), + .out_data(sfc_wr_data), .out_valid(sfc_wr_valid), .out_ready(sfc_wr_ready), + .strobe(set_stb_dsp1), .addr(set_addr_dsp1), .data(set_data_dsp1), + .word00(spi_readback),.word01(32'hffff_ffff),.word02(32'hffff_ffff),.word03(32'hffff_ffff), + .word04(32'hffff_ffff),.word05(32'hffff_ffff),.word06(32'hffff_ffff),.word07(32'hffff_ffff), + .word08(32'hffff_ffff),.word09(gpio_readback),.word10(vita_time[63:32]), + .word11(vita_time[31:0]),.word12(32'hffff_ffff),.word13(irq_readback), + .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]), + .debug(sfc_debug) + ); + */ + assign sfc_debug = 0; + assign set_stb_dsp1 = 0; + assign set_addr_dsp1 = 0; + assign set_data_dsp1 = 0; + assign sfc_rd_ready = 1; + assign sfc_wr_valid = 0; + assign sfc_wr_data = 0; + + setting_reg #(.my_addr(SR_BUF_POOL+1/*same as packet dispatcher*/),.width(1)) sr_clear_sfc + (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.changed(sfc_clear)); + + // Output control lines + wire [7:0] clock_outs, serdes_outs, adc_outs; + assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; + assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; + assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; + + wire phy_reset; + assign PHY_RESETn = ~phy_reset; + + setting_reg #(.my_addr(SR_MISC+0),.width(8)) sr_clk + (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),.in(set_data),.out(clock_outs),.changed()); + + setting_reg #(.my_addr(SR_MISC+1),.width(8)) sr_ser + (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.out(serdes_outs),.changed()); + + setting_reg #(.my_addr(SR_MISC+2),.width(8)) sr_adc + (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.out(adc_outs),.changed()); + + setting_reg #(.my_addr(SR_MISC+4),.width(1)) sr_phy + (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.out(phy_reset),.changed()); + + // ///////////////////////////////////////////////////////////////////////// + // LEDS + // register 8 determines whether leds are controlled by SW or not + // 1 = controlled by HW, 0 = by SW + // In Rev3 there are only 6 leds, and the highest one is on the ETH connector + + wire [7:0] led_src, led_sw; + wire [7:0] led_hw = {run_tx, (run_rx0_d1 | run_rx1_d1), clk_status, serdes_link_up & good_sync, 1'b0}; + + setting_reg #(.my_addr(SR_MISC+3),.width(8)) sr_led + (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.out(led_sw),.changed()); + + setting_reg #(.my_addr(SR_MISC+6),.width(8), .at_reset(8'b0001_1110)) sr_led_src + (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp), .in(set_data_dsp),.out(led_src),.changed()); + + assign leds = (led_src & led_hw) | (~led_src & led_sw); + + // ///////////////////////////////////////////////////////////////////////// + // Interrupt Controller, Slave #8 + + assign irq= {{8'b0}, + {3'b0, uart_tx_int, 2'b0, uart_rx_int}, + {4'b0, clk_status, 3'b0}, + {3'b0, PHY_INTn,i2c_int,spi_int,2'b00}}; + + pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), + .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), + .irq(irq) ); + + // ///////////////////////////////////////////////////////////////////////// + // UART, Slave #10 + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack), + .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i), + .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), + .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); + + // ///////////////////////////////////////////////////////////////////////// + // ADC Frontend + wire [23:0] rx_fe_i, rx_fe_q; + + rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .adc_a({adc_a,2'b00}),.adc_ovf_a(adc_ovf_a), + .adc_b({adc_b,2'b00}),.adc_ovf_b(adc_ovf_b), + .i_out(rx_fe_i), .q_out(rx_fe_q), .run(run_rx0_d1 | run_rx1_d1), .debug()); + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX 0 + wire [31:0] sample_rx0; + wire strobe_rx0, clear_rx0; + + always @(posedge dsp_clk) + run_rx0_d1 <= run_rx0; + + ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0 + (.clk(dsp_clk), .rst(dsp_rst), .clr(clear_rx0), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), + .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q), + .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0), + .debug() ); + + vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE), .DSP_NUMBER(0)) vita_rx_chain0 + (.clk(dsp_clk), .reset(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), + .vita_time(vita_time), .overrun(overrun0), + .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), .clear_o(clear_rx0), + .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o), + .debug() ); + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX 1 + wire [31:0] sample_rx1; + wire strobe_rx1, clear_rx1; + + always @(posedge dsp_clk) + run_rx1_d1 <= run_rx1; + + ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1 + (.clk(dsp_clk), .rst(dsp_rst), .clr(clear_rx1), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), + .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q), + .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1), + .debug() ); + + vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE), .DSP_NUMBER(1)) vita_rx_chain1 + (.clk(dsp_clk), .reset(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), + .vita_time(vita_time), .overrun(overrun1), + .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), .clear_o(clear_rx1), + .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o), + .debug() ); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [35:0] tx_data; + wire tx_src_rdy, tx_dst_rdy; + wire [31:0] debug_vt; + wire clear_tx; + + ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(19)) + ext_fifo_i1 + (.int_clk(dsp_clk), + .ext_clk(clk_to_mac), + .rst(dsp_rst | clear_tx), + .RAM_D_pi(RAM_D_pi), + .RAM_D_po(RAM_D_po), + .RAM_D_poe(RAM_D_poe), + .RAM_A(RAM_A), + .RAM_WEn(RAM_WEn), + .RAM_CENn(RAM_CENn), + .RAM_LDn(RAM_LDn), + .RAM_OEn(RAM_OEn), + .RAM_CE1n(RAM_CE1n), + .datain(rd1_dat), + .src_rdy_i(rd1_ready_o), + .dst_rdy_o(rd1_ready_i), + .dataout(tx_data), + .src_rdy_o(tx_src_rdy), + .dst_rdy_i(tx_dst_rdy), + .debug(debug_extfifo), + .debug2(debug_extfifo2) ); + + wire [23:0] tx_fe_i, tx_fe_q; + wire [31:0] sample_tx; + wire strobe_tx; + + vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(DSP_TX_FIFOSIZE), + .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), + .DSP_NUMBER(0)) + vita_tx_chain + (.clk(dsp_clk), .reset(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), + .sample(sample_tx), .strobe(strobe_tx), + .underrun(underrun), .run(run_tx), .clear_o(clear_tx), + .debug(debug_vt)); + + duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain + (.clk(dsp_clk),.rst(dsp_rst), .clr(clear_tx), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), + .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .debug() ); + + tx_frontend #(.BASE(SR_TX_FRONT)) tx_frontend + (.clk(dsp_clk), .rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(1'b1), + .dac_a(dac_a), .dac_b(dac_b)); + + // /////////////////////////////////////////////////////////////////////////////////// + // SERDES + + serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes + (.clk(dsp_clk),.rst(dsp_rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .rd_dat_i(rd0_dat[31:0]),.rd_flags_i(rd0_dat[35:32]),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .wr_dat_o(wr0_dat[31:0]),.wr_flags_o(wr0_dat[35:32]),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), + .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), + .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), + .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); + + assign RAM_CLK = clk_to_mac; + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing + + wire [31:0] debug_sync; + + time_64bit #(.BASE(SR_TIME64)) time_64bit + (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), + .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), .good_sync(good_sync), .debug(debug_sync)); + + // ///////////////////////////////////////////////////////////////////////////////////////// + // Debug Pins + + assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; + assign debug = 32'd0; + assign debug_gpio_0 = 32'd0; + assign debug_gpio_1 = 32'd0; + +endmodule // u2_core diff --git a/fpga/usrp2/top/USRP2/u2_rev3.ucf b/fpga/usrp2/top/USRP2/u2_rev3.ucf new file mode 100644 index 000000000..8017f61ff --- /dev/null +++ b/fpga/usrp2/top/USRP2/u2_rev3.ucf @@ -0,0 +1,336 @@ +NET "leds[0]" LOC = "E8" ; +NET "leds[1]" LOC = "F7" ; +NET "leds[2]" LOC = "E5" ; +NET "leds[3]" LOC = "B7" ; +NET "leds[4]" LOC = "C11" ; +NET "leds[5]" LOC = "AB19" ; +NET "debug[0]" LOC = "N5" ; +NET "debug[1]" LOC = "N6" ; +NET "debug[2]" LOC = "P1" ; +NET "debug[3]" LOC = "P2" ; +NET "debug[4]" LOC = "P4" ; +NET "debug[5]" LOC = "P5" ; +NET "debug[6]" LOC = "R1" ; +NET "debug[7]" LOC = "R2" ; +NET "debug[8]" LOC = "P6" ; +NET "debug[9]" LOC = "R5" ; +NET "debug[10]" LOC = "R4" ; +NET "debug[11]" LOC = "T3" ; +NET "debug[12]" LOC = "U3" ; +NET "debug[13]" LOC = "M2" ; +NET "debug[14]" LOC = "M3" ; +NET "debug[15]" LOC = "M4" ; +NET "debug[16]" LOC = "M5" ; +NET "debug[17]" LOC = "M6" ; +NET "debug[18]" LOC = "N1" ; +NET "debug[19]" LOC = "N2" ; +NET "debug[20]" LOC = "N3" ; +NET "debug[21]" LOC = "T1" ; +NET "debug[22]" LOC = "T2" ; +NET "debug[23]" LOC = "U2" ; +NET "debug[24]" LOC = "T4" ; +NET "debug[25]" LOC = "U4" ; +NET "debug[26]" LOC = "T5" ; +NET "debug[27]" LOC = "T6" ; +NET "debug[28]" LOC = "U5" ; +NET "debug[29]" LOC = "V5" ; +NET "debug[30]" LOC = "W2" ; +NET "debug[31]" LOC = "W3" ; +NET "debug_clk[0]" LOC = "N4" ; +NET "debug_clk[1]" LOC = "M1" ; +NET "uart_tx_o" LOC = "C7" ; +NET "uart_rx_i" LOC = "A3" ; +NET "exp_time_in_p" LOC = "V3" ; +NET "exp_time_in_n" LOC = "V4" ; +NET "exp_time_out_p" LOC = "V1" ; +NET "exp_time_out_n" LOC = "V2" ; +NET "GMII_COL" LOC = "U16" ; +NET "GMII_CRS" LOC = "U17" ; +NET "GMII_TXD[0]" LOC = "W14" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[1]" LOC = "AA20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[2]" LOC = "AB20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[3]" LOC = "Y18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[4]" LOC = "AA18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[5]" LOC = "AB18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[6]" LOC = "V17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[7]" LOC = "W17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TX_EN" LOC = "Y17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TX_ER" LOC = "V16" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_GTX_CLK" LOC = "AA17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TX_CLK" LOC = "W13" ; +NET "GMII_RXD[0]" LOC = "AA15" ; +NET "GMII_RXD[1]" LOC = "AB15" ; +NET "GMII_RXD[2]" LOC = "U14" ; +NET "GMII_RXD[3]" LOC = "V14" ; +NET "GMII_RXD[4]" LOC = "U13" ; +NET "GMII_RXD[5]" LOC = "V13" ; +NET "GMII_RXD[6]" LOC = "Y13" ; +NET "GMII_RXD[7]" LOC = "AA13" ; +NET "GMII_RX_CLK" LOC = "AA12" ; +NET "GMII_RX_DV" LOC = "AB16" ; +NET "GMII_RX_ER" LOC = "AA16" ; +NET "MDIO" LOC = "Y16" |PULLUP ; +NET "MDC" LOC = "V18" ; +NET "PHY_INTn" LOC = "AB13" ; +NET "PHY_RESETn" LOC = "AA19" ; +NET "PHY_CLK" LOC = "V15" ; +NET "RAM_D[0]" LOC = "N20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[1]" LOC = "N21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[2]" LOC = "N22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[3]" LOC = "M17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[4]" LOC = "M18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[5]" LOC = "M19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[6]" LOC = "M20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[7]" LOC = "M21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[8]" LOC = "M22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[9]" LOC = "Y22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[10]" LOC = "Y21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[11]" LOC = "Y20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[12]" LOC = "Y19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[13]" LOC = "W22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[14]" LOC = "W21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[15]" LOC = "W20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[16]" LOC = "W19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_D[17]" LOC = "V22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[0]" LOC = "U21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[1]" LOC = "T19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[2]" LOC = "V21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[3]" LOC = "V20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[4]" LOC = "T20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[5]" LOC = "T21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[6]" LOC = "T22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[7]" LOC = "T18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[8]" LOC = "R18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[9]" LOC = "P19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[10]" LOC = "P21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[11]" LOC = "P22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[12]" LOC = "N19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[13]" LOC = "N17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[14]" LOC = "N18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[15]" LOC = "T17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[16]" LOC = "U19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[17]" LOC = "U18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_A[18]" LOC = "V19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_CE1n" LOC = "U20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_CENn" LOC = "P18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_CLK" LOC = "P17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_WEn" LOC = "R22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_OEn" LOC = "R21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "RAM_LDn" LOC = "R19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_enable" LOC = "W11" ; +NET "ser_prbsen" LOC = "AA3" ; +NET "ser_loopen" LOC = "Y4" ; +NET "ser_rx_en" LOC = "AB9" ; +NET "ser_tx_clk" LOC = "U7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[0]" LOC = "V7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[1]" LOC = "V10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[2]" LOC = "AB4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[3]" LOC = "AA4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[4]" LOC = "Y5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[5]" LOC = "W5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[6]" LOC = "AB5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[7]" LOC = "AA5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[8]" LOC = "W6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[9]" LOC = "V6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[10]" LOC = "AA6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[11]" LOC = "Y6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[12]" LOC = "W8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[13]" LOC = "V8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[14]" LOC = "AB8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[15]" LOC = "AA8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_tklsb" LOC = "U10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_tkmsb" LOC = "U11" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_rx_clk" LOC = "AA11" ; +NET "ser_r[0]" LOC = "AB10" ; +NET "ser_r[1]" LOC = "AA10" ; +NET "ser_r[2]" LOC = "U9" ; +NET "ser_r[3]" LOC = "U6" ; +NET "ser_r[4]" LOC = "AB11" ; +NET "ser_r[5]" LOC = "Y7" ; +NET "ser_r[6]" LOC = "W7" ; +NET "ser_r[7]" LOC = "AB7" ; +NET "ser_r[8]" LOC = "AA7" ; +NET "ser_r[9]" LOC = "W9" ; +NET "ser_r[10]" LOC = "W10" ; +NET "ser_r[11]" LOC = "Y1" ; +NET "ser_r[12]" LOC = "Y3" ; +NET "ser_r[13]" LOC = "Y2" ; +NET "ser_r[14]" LOC = "W4" ; +NET "ser_r[15]" LOC = "W1" ; +NET "ser_rklsb" LOC = "V9" ; +NET "ser_rkmsb" LOC = "Y10" ; +NET "cpld_start" LOC = "AA9" ; +NET "cpld_mode" LOC = "U12" ; +NET "cpld_done" LOC = "V12" ; +NET "cpld_din" LOC = "AA14" ; +NET "cpld_clk" LOC = "AB14" ; +NET "cpld_detached" LOC = "V11" ; +NET "cpld_init_b" LOC = "W12" ; +NET "cpld_misc" LOC = "Y12" ; +NET "POR" LOC = "W18" ; +NET "WDI" LOC = "W15" ; +NET "adc_a[0]" LOC = "A14" | IOBDELAY= "NONE" ; +NET "adc_a[1]" LOC = "B14" | IOBDELAY= "NONE" ; +NET "adc_a[2]" LOC = "C13" | IOBDELAY= "NONE" ; +NET "adc_a[3]" LOC = "D13" | IOBDELAY= "NONE" ; +NET "adc_a[4]" LOC = "A13" | IOBDELAY= "NONE" ; +NET "adc_a[5]" LOC = "B13" | IOBDELAY= "NONE" ; +NET "adc_a[6]" LOC = "E12" | IOBDELAY= "NONE" ; +NET "adc_a[7]" LOC = "C22" | IOBDELAY= "NONE" ; +NET "adc_a[8]" LOC = "C20" | IOBDELAY= "NONE" ; +NET "adc_a[9]" LOC = "C21" | IOBDELAY= "NONE" ; +NET "adc_a[10]" LOC = "D20" | IOBDELAY= "NONE" ; +NET "adc_a[11]" LOC = "D19" | IOBDELAY= "NONE" ; +NET "adc_a[12]" LOC = "D21" | IOBDELAY= "NONE" ; +NET "adc_a[13]" LOC = "E18" | IOBDELAY= "NONE" ; +NET "adc_ovf_a" LOC = "F18" ; +NET "adc_oen_a" LOC = "E19" ; +NET "adc_pdn_a" LOC = "E20" ; +NET "adc_b[0]" LOC = "A12" | IOBDELAY= "NONE"; +NET "adc_b[1]" LOC = "E16" | IOBDELAY= "NONE" ; +NET "adc_b[2]" LOC = "F12" | IOBDELAY= "NONE" ; +NET "adc_b[3]" LOC = "F13" | IOBDELAY= "NONE" ; +NET "adc_b[4]" LOC = "F16" | IOBDELAY= "NONE" ; +NET "adc_b[5]" LOC = "F17" | IOBDELAY= "NONE" ; +NET "adc_b[6]" LOC = "C19" | IOBDELAY= "NONE" ; +NET "adc_b[7]" LOC = "B20" | IOBDELAY= "NONE" ; +NET "adc_b[8]" LOC = "B19" | IOBDELAY= "NONE" ; +NET "adc_b[9]" LOC = "C18" | IOBDELAY= "NONE" ; +NET "adc_b[10]" LOC = "D18" | IOBDELAY= "NONE" ; +NET "adc_b[11]" LOC = "B18" | IOBDELAY= "NONE" ; +NET "adc_b[12]" LOC = "D17" | IOBDELAY= "NONE" ; +NET "adc_b[13]" LOC = "E17" | IOBDELAY= "NONE" ; +NET "adc_ovf_b" LOC = "B17" ; +NET "adc_oen_b" LOC = "C17" ; +NET "adc_pdn_b" LOC = "D15" ; +NET "dac_a[0]" LOC = "A5" ; +NET "dac_a[1]" LOC = "B5" ; +NET "dac_a[2]" LOC = "C5" ; +NET "dac_a[3]" LOC = "D5" ; +NET "dac_a[4]" LOC = "A4" ; +NET "dac_a[5]" LOC = "B4" ; +NET "dac_a[6]" LOC = "F6" ; +NET "dac_a[7]" LOC = "D10" ; +NET "dac_a[8]" LOC = "D9" ; +NET "dac_a[9]" LOC = "A10" ; +NET "dac_a[10]" LOC = "L2" ; +NET "dac_a[11]" LOC = "L4" ; +NET "dac_a[12]" LOC = "L3" ; +NET "dac_a[13]" LOC = "L6" ; +NET "dac_a[14]" LOC = "L5" ; +NET "dac_a[15]" LOC = "K2" ; +NET "dac_b[0]" LOC = "D11" ; +NET "dac_b[1]" LOC = "E11" ; +NET "dac_b[2]" LOC = "F11" ; +NET "dac_b[3]" LOC = "B10" ; +NET "dac_b[4]" LOC = "C10" ; +NET "dac_b[5]" LOC = "E10" ; +NET "dac_b[6]" LOC = "F10" ; +NET "dac_b[7]" LOC = "A9" ; +NET "dac_b[8]" LOC = "B9" ; +NET "dac_b[9]" LOC = "E9" ; +NET "dac_b[10]" LOC = "F9" ; +NET "dac_b[11]" LOC = "A8" ; +NET "dac_b[12]" LOC = "B8" ; +NET "dac_b[13]" LOC = "D7" ; +NET "dac_b[14]" LOC = "E7" ; +NET "dac_b[15]" LOC = "B6" ; +NET "dac_lock" LOC = "D6" ; +NET "SCL" LOC = "A7" ; +NET "SDA" LOC = "D8" ; +NET "clk_en[0]" LOC = "C4" ; +NET "clk_en[1]" LOC = "D1" ; +NET "clk_sel[0]" LOC = "C3" ; +NET "clk_sel[1]" LOC = "C2" ; +NET "clk_func" LOC = "C12" ; +NET "clk_status" LOC = "B12" ; +NET "clk_fpga_p" LOC = "A11" ; +NET "clk_fpga_n" LOC = "B11" ; +NET "clk_to_mac" LOC = "AB12" ; +NET "pps_in" LOC = "K1" ; +NET "sclk" LOC = "K5" ; +NET "sen_clk" LOC = "K6" ; +NET "sen_dac" LOC = "L1" ; +NET "sdi" LOC = "J1" ; +NET "sdo" LOC = "J2" ; +NET "sen_tx_db" LOC = "C1" ; +NET "sclk_tx_db" LOC = "D3" ; +NET "sdo_tx_db" LOC = "G3" ; +NET "sdi_tx_db" LOC = "G4" ; +NET "sen_tx_adc" LOC = "G2" ; +NET "sclk_tx_adc" LOC = "H1" ; +NET "sdo_tx_adc" LOC = "H2" ; +NET "sdi_tx_adc" LOC = "J4" ; +NET "sen_tx_dac" LOC = "H4" ; +NET "sclk_tx_dac" LOC = "J5" ; +NET "sdi_tx_dac" LOC = "J6" ; +NET "io_tx[0]" LOC = "K4" ; +NET "io_tx[1]" LOC = "K3" ; +NET "io_tx[2]" LOC = "G1" ; +NET "io_tx[3]" LOC = "G5" ; +NET "io_tx[4]" LOC = "H5" ; +NET "io_tx[5]" LOC = "F3" ; +NET "io_tx[6]" LOC = "F2" ; +NET "io_tx[7]" LOC = "F5" ; +NET "io_tx[8]" LOC = "G6" ; +NET "io_tx[9]" LOC = "E2" ; +NET "io_tx[10]" LOC = "E1" ; +NET "io_tx[11]" LOC = "E3" ; +NET "io_tx[12]" LOC = "F4" ; +NET "io_tx[13]" LOC = "D2" ; +NET "io_tx[14]" LOC = "D4" ; +NET "io_tx[15]" LOC = "E4" ; +NET "sen_rx_db" LOC = "D22" ; +NET "sclk_rx_db" LOC = "F19" ; +NET "sdo_rx_db" LOC = "G20" ; +NET "sdi_rx_db" LOC = "H19" ; +NET "sen_rx_adc" LOC = "H18" ; +NET "sclk_rx_adc" LOC = "J17" ; +NET "sdo_rx_adc" LOC = "H21" ; +NET "sdi_rx_adc" LOC = "H22" ; +NET "sen_rx_dac" LOC = "J18" ; +NET "sclk_rx_dac" LOC = "J19" ; +NET "sdi_rx_dac" LOC = "J21" ; +NET "io_rx[0]" LOC = "L21" ; +NET "io_rx[1]" LOC = "L20" ; +NET "io_rx[2]" LOC = "L19" ; +NET "io_rx[3]" LOC = "L18" ; +NET "io_rx[4]" LOC = "L17" ; +NET "io_rx[5]" LOC = "K22" ; +NET "io_rx[6]" LOC = "K21" ; +NET "io_rx[7]" LOC = "K20" ; +NET "io_rx[8]" LOC = "G22" ; +NET "io_rx[9]" LOC = "G21" ; +NET "io_rx[10]" LOC = "F21" ; +NET "io_rx[11]" LOC = "F20" ; +NET "io_rx[12]" LOC = "G19" ; +NET "io_rx[13]" LOC = "G18" ; +NET "io_rx[14]" LOC = "G17" ; +NET "io_rx[15]" LOC = "E22" ; + +NET "clk_to_mac" TNM_NET = "clk_to_mac"; +TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; + +NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; + +NET "cpld_clk" TNM_NET = "cpld_clk"; +TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %; + +NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; +TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; + +NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; +TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; + +NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE; +NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; + +#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; +#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; +#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; + +#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; +#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; + +TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns; diff --git a/fpga/usrp2/top/USRP2/u2_rev3.v b/fpga/usrp2/top/USRP2/u2_rev3.v new file mode 100644 index 000000000..4b0bb5541 --- /dev/null +++ b/fpga/usrp2/top/USRP2/u2_rev3.v @@ -0,0 +1,589 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u2_rev3 + ( + // Misc, debug + output [5:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + output uart_tx_o, + input uart_rx_i, + + // Expansion + input exp_time_in_p, // Diff + input exp_time_in_n, // Diff + output exp_time_out_p, // Diff + output exp_time_out_n, // Diff + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output reg [7:0] GMII_TXD, + output reg GMII_TX_EN, + output reg GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + input PHY_CLK, // possibly use on-board osc + + // RAM + inout [17:0] RAM_D, + output [18:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_CLK, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output reg [15:0] ser_t, + output reg ser_tklsb, + output reg ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // CPLD interface + output cpld_start, // AA9 + output cpld_mode, // U12 + output cpld_done, // V12 + input cpld_din, // AA14 Now shared with CFG_Din + input cpld_clk, // AB14 serial clock + input cpld_detached,// V11 unused + output cpld_init_b, // W12 unused dual purpose + output cpld_misc, // Y12 + + // Watchdog interface + input POR, + output WDI, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_oen_a, + output adc_pdn_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_oen_b, + output adc_pdn_b, + + // DAC + output reg [15:0] dac_a, + output reg [15:0] dac_b, + input dac_lock, // unused for now + + // I2C + inout SCL, + inout SDA, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Clocks + input clk_fpga_p, // Diff + input clk_fpga_n, // Diff + input clk_to_mac, + input pps_in, + + // Generic SPI + output sclk, + output sen_clk, + output sen_dac, + output sdi, + input sdo, + + // TX DBoard + output sen_tx_db, + output sclk_tx_db, + input sdo_tx_db, + output sdi_tx_db, + + output sen_tx_adc, + output sclk_tx_adc, + input sdo_tx_adc, + output sdi_tx_adc, + + output sen_tx_dac, + output sclk_tx_dac, + output sdi_tx_dac, + + inout [15:0] io_tx, + + // RX DBoard + output sen_rx_db, + output sclk_rx_db, + input sdo_rx_db, + output sdi_rx_db, + + output sen_rx_adc, + output sclk_rx_adc, + input sdo_rx_adc, + output sdi_rx_adc, + + output sen_rx_dac, + output sclk_rx_dac, + output sdi_rx_dac, + + inout [15:0] io_rx + ); + + assign cpld_init_b = 0; + // FPGA-specific pins connections + wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; + wire clk90, clk180, clk270; + + // reset the watchdog continuously + reg [15:0] wd; + wire config_success; + + always @(posedge wb_clk) + if(~config_success) + wd <= 0; + else + wd <= wd + 1; + assign WDI = wd[15]; + + wire clk_fpga_unbuf; + + IBUFGDS clk_fpga_pin (.O(clk_fpga_unbuf),.I(clk_fpga_p),.IB(clk_fpga_n)); + BUFG clk_fpga_BUF (.O(clk_fpga),.I(clk_fpga_unbuf)); + + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + wire cpld_clock_buf; + BUFG cpld_clock_BUF (.O(cpld_clock_buf),.I(cpld_clock)); + + wire exp_time_in; + IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); + defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_time_out; + OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); + defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; + + reg [5:0] clock_ready_d; + always @(posedge clk_fpga) + clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; + wire dcm_rst = ~&clock_ready_d & |clock_ready_d; + + wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b; + assign adc_oen_a = ~adc_oe_a; + assign adc_oen_b = ~adc_oe_b; + assign adc_pdn_a = ~adc_on_a; + assign adc_pdn_b = ~adc_on_b; + + reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2; + reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2; + + // ADC A and B are swapped in schematic to facilitate clean layout + always @(posedge dsp_clk) + begin + adc_a_reg1 <= adc_b; + adc_b_reg1 <= adc_a; + adc_ovf_a_reg1 <= adc_ovf_b; + adc_ovf_b_reg1 <= adc_ovf_a; + end + + always @(posedge dsp_clk) + begin + adc_a_reg2 <= adc_a_reg1; + adc_b_reg2 <= adc_b_reg1; + adc_ovf_a_reg2 <= adc_ovf_a_reg1; + adc_ovf_b_reg2 <= adc_ovf_b_reg1; + end // always @ (posedge dsp_clk) + + // Handle Clocks + DCM DCM_INST (.CLKFB(dsp_clk), + .CLKIN(clk_fpga), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(clk90), + .CLK180(clk180), + .CLK270(clk270), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 10.000; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // LEDs are active low outputs + wire [5:0] leds_int; + assign leds = 6'b011111 ^ leds_int; // all except eth are active-low + + // SPI + wire miso, mosi, sclk_int; + assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0; + + assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) | + (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) | + (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc); + + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; + wire [7:0] GMII_TXD_unreg; + wire GMII_GTX_CLK_int; + + always @(posedge GMII_GTX_CLK_int) + begin + GMII_TX_EN <= GMII_TX_EN_unreg; + GMII_TX_ER <= GMII_TX_ER_unreg; + GMII_TXD <= GMII_TXD_unreg; + end + + OFDDRRSE OFDDRRSE_gmii_inst + (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) + .C0(GMII_GTX_CLK_int), // 0 degree clock input + .C1(~GMII_GTX_CLK_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + + wire ser_tklsb_unreg, ser_tkmsb_unreg; + wire [15:0] ser_t_unreg; + wire ser_tx_clk_int; + + always @(posedge ser_tx_clk_int) + begin + ser_tklsb <= ser_tklsb_unreg; + ser_tkmsb <= ser_tkmsb_unreg; + ser_t <= ser_t_unreg; + end + + assign ser_tx_clk = clk_fpga; + + reg [15:0] ser_r_int; + reg ser_rklsb_int, ser_rkmsb_int; + + wire ser_rx_clk_buf; + BUFG ser_rx_clk_BUF (.O(ser_rx_clk_buf),.I(ser_rx_clk)); + always @(posedge ser_rx_clk_buf) + begin + ser_r_int <= ser_r; + ser_rklsb_int <= ser_rklsb; + ser_rkmsb_int <= ser_rkmsb; + end + + wire [15:0] dac_a_int, dac_b_int; + // DAC A and B are swapped in schematic to facilitate clean layout + // DAC A is also inverted in schematic to facilitate clean layout + always @(posedge dsp_clk) dac_a <= ~dac_b_int; + always @(posedge dsp_clk) dac_b <= dac_a_int; + + /* + OFDDRRSE OFDDRRSE_serdes_inst + (.Q(ser_tx_clk), // Data output (connect directly to top-level port) + .C0(ser_tx_clk_int), // 0 degree clock input + .C1(~ser_tx_clk_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + */ + + wire [17:0] RAM_D_pi; + wire [17:0] RAM_D_po; + wire RAM_D_poe; + + genvar i; + + // + // Instantiate IO for Bidirectional bus to SRAM + // + + generate + for (i=0;i<18;i=i+1) + begin : gen_RAM_D_IO + + IOBUF #( + .DRIVE(12), + .IOSTANDARD("LVCMOS25"), + .SLEW("FAST") + ) + RAM_D_i ( + .O(RAM_D_pi[i]), + .I(RAM_D_po[i]), + .IO(RAM_D[i]), + .T(RAM_D_poe) + ); + end // block: gen_RAM_D_IO + endgenerate + + // + // DCM edits start here + // + + + wire RAM_CLK_buf; + wire clk_to_mac_buf; + wire clk125_ext_clk0; + wire clk125_ext_clk180; + wire clk125_ext_clk0_buf; + wire clk125_ext_clk180_buf; + wire clk125_int_buf; + wire clk125_int; + + IBUFG clk_to_mac_buf_i1 (.I(clk_to_mac), + .O(clk_to_mac_buf)); + + DCM DCM_INST1 (.CLKFB(RAM_CLK_buf), + .CLKIN(clk_to_mac_buf), + .DSSEN(1'b0), + .PSCLK(1'b0), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .RST(1'b0), + .CLK0(clk125_ext_clk0), + .CLK180(clk125_ext_clk180) ); + defparam DCM_INST1.CLK_FEEDBACK = "1X"; + defparam DCM_INST1.CLKDV_DIVIDE = 2.0; + defparam DCM_INST1.CLKFX_DIVIDE = 1; + defparam DCM_INST1.CLKFX_MULTIPLY = 4; + defparam DCM_INST1.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST1.CLKIN_PERIOD = 8.000; + defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "FIXED"; + defparam DCM_INST1.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST1.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST1.FACTORY_JF = 16'h8080; + defparam DCM_INST1.PHASE_SHIFT = -64; + defparam DCM_INST1.STARTUP_WAIT = "FALSE"; + + IBUFG RAM_CLK_buf_i1 (.I(RAM_CLK), + .O(RAM_CLK_buf)); + BUFG clk125_ext_clk0_buf_i1 (.I(clk125_ext_clk0), + .O(clk125_ext_clk0_buf)); + BUFG clk125_ext_clk180_buf_i1 (.I(clk125_ext_clk180), + .O(clk125_ext_clk180_buf)); + + OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK), + .C0(clk125_ext_clk0_buf), + .C1(clk125_ext_clk180_buf), + .CE(1'b1), + .D0(1'b1), + .D1(1'b0), + .R(1'b0), + .S(1'b0)); + +// SRL16 dcm2_rst_i1 (.D(1'b0), +// .CLK(clk_to_mac_buf), +// .Q(dcm2_rst), +// .A0(1'b1), +// .A1(1'b1), +// .A2(1'b1), +// .A3(1'b1)); + // synthesis attribute init of dcm2_rst_i1 is "000F"; + + DCM DCM_INST2 (.CLKFB(clk125_int_buf), + .CLKIN(clk_to_mac_buf), + .DSSEN(1'b0), + .PSCLK(1'b0), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .RST(1'b0), + .CLK0(clk125_int)); + defparam DCM_INST2.CLK_FEEDBACK = "1X"; + defparam DCM_INST2.CLKDV_DIVIDE = 2.0; + defparam DCM_INST2.CLKFX_DIVIDE = 1; + defparam DCM_INST2.CLKFX_MULTIPLY = 4; + defparam DCM_INST2.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST2.CLKIN_PERIOD = 8.000; + defparam DCM_INST2.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST2.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST2.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST2.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST2.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST2.FACTORY_JF = 16'h8080; + defparam DCM_INST2.PHASE_SHIFT = 0; + defparam DCM_INST2.STARTUP_WAIT = "FALSE"; + + BUFG clk125_int_buf_i1 (.I(clk125_int), + .O(clk125_int_buf)); + + // + // DCM edits end here + // + + + u2_core + u2_core(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk125_int_buf), + .pps_in (pps_in), + .leds (leds_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_time_in (exp_time_in), + .exp_time_out (exp_time_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk_buf), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .cpld_misc (cpld_misc), + .cpld_init_b (cpld_init_b), + .por (~POR), + .config_success (config_success), + .adc_a (adc_a_reg2), + .adc_ovf_a (adc_ovf_a_reg2), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b_reg2), + .adc_ovf_b (adc_ovf_b_reg2), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (dac_a_int), + .dac_b (dac_b_int), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk_int), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D_pi (RAM_D_pi), + .RAM_D_po (RAM_D_po), + .RAM_D_poe (RAM_D_poe), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + // .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (uart_tx_o), + .uart_rx_i (uart_rx_i), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2) + ); + +endmodule // u2_rev2 diff --git a/fpga/usrp2/top/extract_usage.py b/fpga/usrp2/top/extract_usage.py new file mode 100755 index 000000000..55fbf384c --- /dev/null +++ b/fpga/usrp2/top/extract_usage.py @@ -0,0 +1,60 @@ +#!/usr/bin/env python +# +# Copyright 2012 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +import os +import sys + +ALL_MAP_FILES = """\ +./N2x0/build-N210R4/u2plus_map.map N210 +./N2x0/build-N200R4/u2plus_map.map N200 +./USRP2/build/u2_rev3_map.map USRP2 +./E1x0/build-E100/u1e_map.map E100 +./E1x0/build-E110/u1e_map.map E110 +./B100/build-B100/B100_map.map B100 +""" + +def extract_map_from_file(path): + output = '' + found = False + for line in open(path).readlines(): + if line.strip() == 'Mapping completed.': found = False + if line.strip() == 'Logic Utilization:': found = True + if found: output += line + return output + +def extract_maps(): + output = '' + for line in ALL_MAP_FILES.splitlines(): + path, name = line.split() + if not os.path.exists(path): + print 'DNE ', path, ' skipping...' + output += """ + + + +######################################################################## +## %s Usage Summary +######################################################################## + +%s"""%(name, extract_map_from_file(path).strip()) + return output + '\n\n' + +if __name__ == '__main__': + summary = extract_maps() + if len(sys.argv) == 1: print summary + else: open(sys.argv[1], 'w').write(summary) diff --git a/fpga/usrp2/top/python/check_inout.py b/fpga/usrp2/top/python/check_inout.py new file mode 100755 index 000000000..ff371d378 --- /dev/null +++ b/fpga/usrp2/top/python/check_inout.py @@ -0,0 +1,62 @@ +#!/usr/bin/env python +# +# Copyright 2010 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +# Description: +# generates a list of inputs and outputs from the top-level Verilog file and cross-references them to the .ucf. +# outputs errors for pins that aren't found in the UCF, checks for capitalization errors and other common mistakes + +import sys +import re + +if __name__=='__main__': + if len(sys.argv) == 2: + print "Usage: %s <top level Verilog file> <pin definition UCF>" + sys.exit(-1) + + verilog_filename = sys.argv[1] + ucf_filename = sys.argv[2] + + verilog_file = open(verilog_filename, 'r') + ucf_file = open(ucf_filename, 'r') + + verilog_iolist = list() + ucf_iolist = list() + + #read in all input, inout, and output declarations and compile a list + for line in verilog_file: + for match in re.findall(r"(?:input|inout|output) (?:reg )*(?:\[.*\] )*(\w+)", line.split("//")[0]): + verilog_iolist.append(match) + + for line in ucf_file: + m = re.search(r"""NET "(\w+).*" """, line.split("#")[0]) + if m is not None: + ucf_iolist.append(m.group(1)) + + #now find corresponding matches and error when you don't find one + #we search for .v defs without matching .ucf defs since the reverse isn't necessarily a problem + err = False + + for item in verilog_iolist: + if item not in ucf_iolist: + print "Error: %s appears in the top-level Verilog file, but is not in the UCF definition file!" % item + err = True + + if err: + sys.exit(-1) + + print "No errors found." + sys.exit(0) diff --git a/fpga/usrp2/top/python/check_timing.py b/fpga/usrp2/top/python/check_timing.py new file mode 100755 index 000000000..0c5918096 --- /dev/null +++ b/fpga/usrp2/top/python/check_timing.py @@ -0,0 +1,33 @@ +#!/usr/bin/env python +# +# Copyright 2011 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. + +import sys +import re + +def print_timing_constraint_summary(twr_file): + output = "" + keep = False + done = False + for line in open(twr_file).readlines(): + if 'Derived Constraint Report' in line: keep = True + if 'constraint' in line and 'met' in line: done = True + if not keep and done: keep = True + if keep: output += line + if done: break + print("\n\n"+output) + +if __name__=='__main__': map(print_timing_constraint_summary, sys.argv[1:]) diff --git a/fpga/usrp2/top/tcl/ise_helper.tcl b/fpga/usrp2/top/tcl/ise_helper.tcl new file mode 100644 index 000000000..c5ceded1b --- /dev/null +++ b/fpga/usrp2/top/tcl/ise_helper.tcl @@ -0,0 +1,94 @@ +# +# Copyright 2008 Ettus Research LLC +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +proc set_props {process options} { + if ![string compare $options ""] { + return + } + set state 1 + foreach opt $options { + if $state { + set key $opt + set state 0 + } else { + puts ">>> Setting: $process\[$key\] = $opt" + if ![string compare $process "Project"] { + project set $key $opt + } else { + project set $key $opt -process $process + } + set state 1 + } + } +} + +if [file isfile $env(ISE_FILE)] { + puts ">>> Opening project: $env(ISE_FILE)" + project open $env(ISE_FILE) +} else { + puts ">>> Creating project: $env(ISE_FILE)" + project new $env(ISE_FILE) + + ################################################## + # Set the project properties + ################################################## + set_props "Project" $env(PROJECT_PROPERTIES) + + ################################################## + # Add the sources + ################################################## + foreach source $env(SOURCES) { + puts ">>> Adding source to project: $source" + xfile add $source + } + + ################################################## + # Add the custom sources + ################################################## + foreach source $env(CUSTOM_SRCS) { + puts ">>> Adding custom source to project: $source" + xfile add $source -include_global + } + + ################################################## + # Set the top level module + ################################################## + project set top $env(TOP_MODULE) + + ################################################## + # Set the process properties + ################################################## + set_props "Synthesize - XST" $env(SYNTHESIZE_PROPERTIES) + set_props "Translate" $env(TRANSLATE_PROPERTIES) + set_props "Map" $env(MAP_PROPERTIES) + set_props "Place & Route" $env(PLACE_ROUTE_PROPERTIES) + set_props "Generate Post-Place & Route Static Timing" $env(STATIC_TIMING_PROPERTIES) + set_props "Generate Programming File" $env(GEN_PROG_FILE_PROPERTIES) + set_props "Generate Post-Place & Route Simulation Model" $env(SIM_MODEL_PROPERTIES) +} + +if [string compare [lindex $argv 0] ""] { + puts ">>> Running Process: [lindex $argv 0]" + process run [lindex $argv 0] +} + +project close +exit + + |