diff options
Diffstat (limited to 'fpga/usrp2/gpif')
| -rw-r--r-- | fpga/usrp2/gpif/fifo36_to_gpmc16.v | 27 | ||||
| -rw-r--r-- | fpga/usrp2/gpif/slave_fifo.v | 8 |
2 files changed, 27 insertions, 8 deletions
diff --git a/fpga/usrp2/gpif/fifo36_to_gpmc16.v b/fpga/usrp2/gpif/fifo36_to_gpmc16.v index 508cd319c..4b4dc3109 100644 --- a/fpga/usrp2/gpif/fifo36_to_gpmc16.v +++ b/fpga/usrp2/gpif/fifo36_to_gpmc16.v @@ -17,7 +17,10 @@ module fifo36_to_gpmc16 #( - parameter FIFO_SIZE = 9 + parameter FIFO_SIZE = 9, + + //not ready until minimum xfers of occupancy available + parameter MIN_OCC16 = 2 ) ( //input fifo interface @@ -31,22 +34,36 @@ module fifo36_to_gpmc16 output [15:0] out_data, output valid, input enable, - output eof + output eof, + output reg has_data ); + wire [15:0] fifo_occ; + + always @(posedge gpif_clk) + has_data <= (fifo_occ >= MIN_OCC16); + wire [35:0] data_int; wire src_rdy_int, dst_rdy_int; - fifo_2clock_cascade #(.WIDTH(36), .SIZE(FIFO_SIZE)) fifo_2clk + fifo_2clock_cascade #(.WIDTH(36), .SIZE(6)) fifo_2clk (.wclk(fifo_clk), .datain(in_data), .src_rdy_i(in_src_rdy), .dst_rdy_o(in_dst_rdy), .space(), .rclk(gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(), .arst(fifo_rst | gpif_rst)); - wire [18:0] data18_int; + wire [18:0] data19_int; + wire data19_src_rdy_int, data19_dst_rdy_int; + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 (.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0), .f36_datain(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int), - .f19_dataout(data18_int), .f19_src_rdy_o(valid), .f19_dst_rdy_i(enable) ); + .f19_dataout(data19_int), .f19_src_rdy_o(data19_src_rdy_int), .f19_dst_rdy_i(data19_dst_rdy_int) ); + + wire [17:0] data18_int; + fifo_cascade #(.WIDTH(18), .SIZE(FIFO_SIZE+1)) occ_ctrl_fifo + (.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0), + .datain(data19_int[17:0]), .src_rdy_i(data19_src_rdy_int), .dst_rdy_o(data19_dst_rdy_int), .space(), + .dataout(data18_int), .src_rdy_o(valid), .dst_rdy_i(enable), .occupied(fifo_occ)); assign out_data = data18_int[15:0]; assign eof = data18_int[17]; diff --git a/fpga/usrp2/gpif/slave_fifo.v b/fpga/usrp2/gpif/slave_fifo.v index 0f301f8a6..c10b79ab4 100644 --- a/fpga/usrp2/gpif/slave_fifo.v +++ b/fpga/usrp2/gpif/slave_fifo.v @@ -70,6 +70,7 @@ module slave_fifo reg tx_valid, ctrl_valid; wire tx_ready, ctrl_ready; reg rx_enable, resp_enable; + wire rx_data_enough_occ; reg [9:0] transfer_count; //number of lines (a line is 16 bits) in active transfer @@ -145,7 +146,7 @@ module slave_fifo fifoadr <= 2'b00; sloe <= 0; end - else if(rx_valid & ~FX2_DF & last_data_bus_hog == BUS_HOG_TX) begin //if the data fifo has data and the FX2 isn't full + else if(rx_data_enough_occ & ~FX2_DF & last_data_bus_hog == BUS_HOG_TX) begin //if the data fifo has data and the FX2 isn't full state <= STATE_DATA_RX_ADR; last_data_bus_hog <= BUS_HOG_RX; fifoadr <= 2'b10; @@ -156,7 +157,7 @@ module slave_fifo fifoadr <= 2'b00; sloe <= 0; end - else if(rx_valid & ~FX2_DF) begin + else if(rx_data_enough_occ & ~FX2_DF) begin state <= STATE_DATA_RX_ADR; last_data_bus_hog <= BUS_HOG_RX; fifoadr <= 2'b10; @@ -241,10 +242,11 @@ module slave_fifo // //////////////////////////////////////////// // RX Data Path - fifo36_to_gpmc16 #(.FIFO_SIZE(DATA_RX_FIFO_SIZE)) fifo36_to_gpmc16_rx( + fifo36_to_gpmc16 #(.FIFO_SIZE(DATA_RX_FIFO_SIZE), .MIN_OCC16(DATA_XFER_COUNT)) fifo36_to_gpmc16_rx( .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), .in_data(rx_data), .in_src_rdy(rx_src_rdy), .in_dst_rdy(rx_dst_rdy), .gpif_clk(gpif_clk), .gpif_rst(gpif_rst), + .has_data(rx_data_enough_occ), .out_data(gpif_d_out_data), .valid(rx_valid), .enable(rx_enable) ); |