diff options
4 files changed, 51 insertions, 66 deletions
diff --git a/fpga/usrp3/lib/packet_proc/ip_hdr_checksum.v b/fpga/usrp3/lib/packet_proc/ip_hdr_checksum.v index 7e2e0f88e..bf789f94c 100644 --- a/fpga/usrp3/lib/packet_proc/ip_hdr_checksum.v +++ b/fpga/usrp3/lib/packet_proc/ip_hdr_checksum.v @@ -1,29 +1,56 @@ // -// Copyright 2014 Ettus Research LLC -// Copyright 2018 Ettus Research, a National Instruments Company +// Copyright 2020 Ettus Research, a National Instruments Brand // // SPDX-License-Identifier: LGPL-3.0-or-later // -// Compute IP header checksum. 2 cycles of latency. -module ip_hdr_checksum - (input clk, input [159:0] in, output reg [15:0] out); +// Description: +// Compute IP header checksum. 0-2 cycles of latency. +// +// Parameter: +// LATENCY : sets how many pipeline stages are inserted +// 0 - No pipelining +// 1 - output Flop +// 2 - output + gen_sum Flop +// + +module ip_hdr_checksum #( + parameter LATENCY = 2 +) ( + input clk, input [159:0] in, output reg [15:0] out, input clken +); - wire [18:0] padded [0:9]; - reg [18:0] sum_a, sum_b; + wire [18:0] padded [0:9]; - genvar i; - generate - for(i=0 ; i<10 ; i=i+1) + genvar i; + generate + for(i=0 ; i<10 ; i=i+1) assign padded[i] = {3'b000,in[i*16+15:i*16]}; - endgenerate + endgenerate - always @(posedge clk) sum_a = padded[0] + padded[1] + padded[2] + padded[3] + padded[4]; - always @(posedge clk) sum_b = padded[5] + padded[6] + padded[7] + padded[8] + padded[9]; + wire [18:0] sum_a_d, sum_b_d; + reg [18:0] sum_a_q, sum_b_q; - wire [18:0] sum = sum_a + sum_b; + assign sum_a_d = padded[0] + padded[1] + padded[2] + padded[3] + padded[4]; + assign sum_b_d = padded[5] + padded[6] + padded[7] + padded[8] + padded[9]; + + if (LATENCY >= 1) begin : gen_sum_ff + always @(posedge clk) if (clken) sum_a_q <= sum_a_d; + always @(posedge clk) if (clken) sum_b_q <= sum_b_d; + end else begin : gen_sum_comb + always @(sum_a_d) sum_a_q = sum_a_d; + always @(sum_b_d) sum_b_q = sum_b_d; + end + + wire [18:0] sum; + wire [15:0] out_d; + + assign sum = sum_a_q + sum_b_q; + assign out_d = ~(sum[15:0] + {13'd0,sum[18:16]}); + + if (LATENCY >= 2) begin : gen_out_ff + always @(posedge clk) if (clken) out <= out_d; + end else begin : gen_out_comb + always @(out_d) out = out_d; + end - always @(posedge clk) - out <= ~(sum[15:0] + {13'd0,sum[18:16]}); - - endmodule // ip_hdr_checksum diff --git a/fpga/usrp3/lib/packet_proc/ip_hdr_checksum_tb.v b/fpga/usrp3/lib/packet_proc/ip_hdr_checksum_tb.v deleted file mode 100644 index de52a0049..000000000 --- a/fpga/usrp3/lib/packet_proc/ip_hdr_checksum_tb.v +++ /dev/null @@ -1,43 +0,0 @@ -// -// Copyright 2013 Ettus Research, a National Instruments Company -// -// SPDX-License-Identifier: LGPL-3.0-or-later -// - -module ip_hdr_checksum_tb(); - - initial $dumpfile("ip_hdr_checksum_tb.vcd"); - initial $dumpvars(0,ip_hdr_checksum_tb); - - reg clk; - - wire [159:0] in = { - 16'h4500, - 16'h0030, - 16'h4422, - 16'h4000, - 16'h8006, - 16'h0000, - 16'h8c7c, - 16'h19ac, - 16'hae24, - 16'h1e2b - }; - - wire [15:0] out; - ip_hdr_checksum ip_hdr_checksum - (.clk(clk), - .in(in), - .out(out)); - - initial - begin - clk <= 0; - #100 clk <= 1; - #100 clk <= 0; - #100 clk <= 1; - #100 $display("Computed 0x%x, should be 0x442e", out); - #100 $finish; - end - -endmodule // ip_hdr_checksum_tb diff --git a/fpga/usrp3/lib/rfnoc/xport/eth_ipv4_chdr64_adapter.v b/fpga/usrp3/lib/rfnoc/xport/eth_ipv4_chdr64_adapter.v index f05c211b1..2f30b1565 100644 --- a/fpga/usrp3/lib/rfnoc/xport/eth_ipv4_chdr64_adapter.v +++ b/fpga/usrp3/lib/rfnoc/xport/eth_ipv4_chdr64_adapter.v @@ -324,8 +324,8 @@ module eth_ipv4_chdr64_adapter #( wire [15:0] udp_checksum = 16'h0; ip_hdr_checksum ip_hdr_checksum ( - .clk(clk), .in({misc_ip, ip_len, ident, flag_frag, ttl_prot, 16'd0, my_ipv4_addr, ip_dst}), - .out(iphdr_checksum) + .clk(clk), .in({misc_ip, ip_len, ident, flag_frag, ttl_prot, 16'd0, + my_ipv4_addr, ip_dst}), .clken(1'b1), .out(iphdr_checksum) ); always @(*) begin diff --git a/fpga/usrp3/lib/sim/packet_proc/ip_hdr_checksum/ip_hdr_checksum_tb.v b/fpga/usrp3/lib/sim/packet_proc/ip_hdr_checksum/ip_hdr_checksum_tb.v index 82deca656..191a62f0a 100644 --- a/fpga/usrp3/lib/sim/packet_proc/ip_hdr_checksum/ip_hdr_checksum_tb.v +++ b/fpga/usrp3/lib/sim/packet_proc/ip_hdr_checksum/ip_hdr_checksum_tb.v @@ -1,9 +1,9 @@ // -// Copyright 2014 Ettus Research LLC -// Copyright 2018 Ettus Research, a National Instruments Company +// Copyright 2020 Ettus Research, a National Instruments Brand // // SPDX-License-Identifier: LGPL-3.0-or-later // + module ip_hdr_checksum_tb(); initial $dumpfile("ip_hdr_checksum_tb.vcd"); @@ -28,7 +28,8 @@ module ip_hdr_checksum_tb(); ip_hdr_checksum ip_hdr_checksum (.clk(clk), .in(in), - .out(out)); + .out(out), + .clken(1)); initial begin |