diff options
| -rw-r--r-- | usrp2/top/u2plus/u2plus.v | 1 | ||||
| -rw-r--r-- | usrp2/top/u2plus/u2plus_core.v | 5 |
2 files changed, 4 insertions, 2 deletions
diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index ac0f6bbd1..1feed1314 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -369,6 +369,7 @@ module u2plus .uart_baud_o (), .sim_mode (1'b0), .clock_divider (2), + .button (FPGA_RESET), .spiflash_cs (flash_cs), .spiflash_clk (flash_clk), .spiflash_miso (flash_miso), diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 0470e6e9e..fa3fd9ff0 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -124,7 +124,8 @@ module u2plus_core output uart_baud_o, input sim_mode, input [3:0] clock_divider, - + input button, + output spiflash_cs, output spiflash_clk, input spiflash_miso, output spiflash_mosi ); @@ -473,7 +474,7 @@ defparam bootram.RAM0.INIT_01=256'ha48500ff_b810ffd0_f880200c_30a50001_10830000_ assign irq= {{8'b0}, {8'b0}, - {3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, + {2'b0, button, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}}; pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]), |