diff options
| -rw-r--r-- | usrp2/gpif/gpif.v | 110 | ||||
| -rwxr-xr-x | usrp2/top/u1plus/core_compile | 3 | ||||
| -rw-r--r-- | usrp2/top/u1plus/u1plus_core.v | 26 |
3 files changed, 111 insertions, 28 deletions
diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index 14ed2690f..e72490b17 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -17,7 +17,9 @@ module gpif input fifo_clk, input fifo_rst, input clear_tx, input clear_rx, output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, - + + output tx_underrun, output rx_overrun, + input [7:0] test_rate, input [3:0] test_ctrl, output [31:0] debug0, output [31:0] debug1 ); @@ -38,12 +40,12 @@ module gpif wire [31:0] debug_rd, debug_wr; // //////////////////////////////////////////////////////////////////// - // TX Side - + // TX Data Path + wire [18:0] tx19_data; wire tx19_src_rdy, tx19_dst_rdy; - wire [35:0] tx36_data; - wire tx36_src_rdy, tx36_dst_rdy; + wire [35:0] tx36_data, tx_data; + wire tx36_src_rdy, tx36_dst_rdy, tx_src_rdy, tx_dst_rdy; wire [18:0] ctrl_data; wire ctrl_src_rdy, ctrl_dst_rdy; @@ -64,27 +66,27 @@ module gpif .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy), - .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i)); + .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy)); - // //////////////////////////////////////////////////////////////////// - // RX Side + // //////////////////////////////////////////// + // RX Data Path - wire [35:0] rx36_data; - wire rx36_src_rdy, rx36_dst_rdy; + wire [35:0] rx36_data, rx_data; + wire rx36_src_rdy, rx36_dst_rdy, rx_src_rdy, rx_dst_rdy; wire [18:0] rx19_data; wire rx19_src_rdy, rx19_dst_rdy; wire [18:0] resp_data, resp_int; wire resp_src_rdy, resp_dst_rdy, resp_src_rdy_int, resp_dst_rdy_int; fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .datain(rx_data), .src_rdy_i(rx_src_rdy), .dst_rdy_o(rx_dst_rdy), .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // FIXME Endianness? - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), .f19_dataout(rx19_data), .f19_src_rdy_o(rx19_src_rdy), .f19_dst_rdy_i(rx19_dst_rdy) ); @@ -115,14 +117,84 @@ module gpif .data_i(resp_int), .src_rdy_i(resp_src_rdy_int), .dst_rdy_o(resp_dst_rdy_int), .data_o(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy)); + // //////////////////////////////////////////////////////////////////// + // Debug support, timed and loopback + // RX side muxes test data into the same stream + wire [35:0] timedrx_data, loopbackrx_data, testrx_data; + wire [35:0] timedtx_data, loopbacktx_data, testtx_data; + wire timedrx_src_rdy, timedrx_dst_rdy, loopbackrx_src_rdy, loopbackrx_dst_rdy, + testrx_src_rdy, testrx_dst_rdy; + wire timedtx_src_rdy, timedtx_dst_rdy, loopbacktx_src_rdy, loopbacktx_dst_rdy, + testtx_src_rdy, testtx_dst_rdy; + wire timedrx_src_rdy_int, timedrx_dst_rdy_int, timedtx_src_rdy_int, timedtx_dst_rdy_int; + + wire [31:0] total, crc_err, seq_err, len_err; + wire sel_testtx = test_ctrl[0]; + wire sel_loopbacktx = test_ctrl[1]; + wire pkt_src_enable = test_ctrl[2]; + wire pkt_sink_enable = test_ctrl[3]; + + fifo36_mux rx_test_mux_lvl_1 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .data0_i(timedrx_data), .src0_rdy_i(timedrx_src_rdy), .dst0_rdy_o(timedrx_dst_rdy), + .data1_i(loopbackrx_data), .src1_rdy_i(loopbackrx_src_rdy), .dst1_rdy_o(loopbackrx_dst_rdy), + .data_o(testrx_data), .src_rdy_o(testrx_src_rdy), .dst_rdy_i(testrx_dst_rdy)); + + fifo36_mux rx_test_mux_lvl_2 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .data0_i(testrx_data), .src0_rdy_i(testrx_src_rdy), .dst0_rdy_o(testrx_dst_rdy), + .data1_i(rx_data_i), .src1_rdy_i(rx_src_rdy_i), .dst1_rdy_o(rx_dst_rdy_o), + .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + + fifo_short #(.WIDTH(36)) loopback_fifo + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx | clear_rx), + .datain(loopbacktx_data), .src_rdy_i(loopbacktx_src_rdy), .dst_rdy_o(loopbacktx_dst_rdy), + .dataout(loopbackrx_data), .src_rdy_o(loopbackrx_src_rdy), .dst_rdy_i(loopbackrx_dst_rdy)); + + // Crossbar used as a demux for switching TX stream to main DSP or to test logic + crossbar36 tx_crossbar_lvl_1 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .cross(sel_testtx), + .data0_i(tx_data), .src0_rdy_i(tx_src_rdy), .dst0_rdy_o(tx_dst_rdy), + .data1_i(tx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(), // No 2nd input + .data0_o(tx_data_o), .src0_rdy_o(tx_src_rdy_o), .dst0_rdy_i(tx_dst_rdy_i), + .data1_o(testtx_data), .src1_rdy_o(testtx_src_rdy), .dst1_rdy_i(testtx_dst_rdy) ); + + crossbar36 tx_crossbar_lvl_2 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .cross(sel_loopbacktx), + .data0_i(testtx_data), .src0_rdy_i(testtx_src_rdy), .dst0_rdy_o(testtx_dst_rdy), + .data1_i(testtx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(), // No 2nd input + .data0_o(timedtx_data), .src0_rdy_o(timedtx_src_rdy), .dst0_rdy_i(timedtx_dst_rdy), + .data1_o(loopbacktx_data), .src1_rdy_o(loopbacktx_src_rdy), .dst1_rdy_i(loopbacktx_dst_rdy) ); + + // Fixed rate TX traffic consumer + fifo_pacer tx_pacer + (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_sink_enable), + .src1_rdy_i(timedtx_src_rdy), .dst1_rdy_o(timedtx_dst_rdy), + .src2_rdy_o(timedtx_src_rdy_int), .dst2_rdy_i(timedtx_dst_rdy_int), + .underrun(tx_underrun), .overrun()); + + packet_verifier32 pktver32 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .data_i(timedtx_data), .src_rdy_i(timedtx_src_rdy_int), .dst_rdy_o(timedtx_dst_rdy_int), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + + // Fixed rate RX traffic generator + packet_generator32 pktgen32 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .header({len_err,seq_err,crc_err,total}), + .data_o(timedrx_data), .src_rdy_o(timedrx_src_rdy_int), .dst_rdy_i(timedrx_dst_rdy_int)); + + fifo_pacer rx_pacer + (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_src_enable), + .src1_rdy_i(timedrx_src_rdy_int), .dst1_rdy_o(timedrx_dst_rdy_int), + .src2_rdy_o(timedrx_src_rdy), .dst2_rdy_i(timedrx_dst_rdy), + .underrun(), .overrun(rx_overrun)); + // //////////////////////////////////////////// // DEBUG - // Loopback for testing - //assign resp_data = ctrl_data; - //assign resp_src_rdy = ctrl_src_rdy; - //assign ctrl_dst_rdy = resp_dst_rdy; - assign debug0 = { 5'd0, gpif_misc[2:0], gpif_ctl[3:0], gpif_rdy[3:0], gpif_d_copy[15:0] }; assign debug1 = { { debug_rd[15:8] }, { debug_rd[7:0] }, diff --git a/usrp2/top/u1plus/core_compile b/usrp2/top/u1plus/core_compile index 0d95f704d..b2ccc8b49 100755 --- a/usrp2/top/u1plus/core_compile +++ b/usrp2/top/u1plus/core_compile @@ -1,2 +1 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ u1plus_core.v 2>&1 - +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index 8e83c01ff..75845e8f4 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -13,6 +13,7 @@ module u1plus_core output sclk, output [15:0] sen, output mosi, input miso, input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, + output tx_underrun, output rx_overrun, inout [15:0] io_tx, inout [15:0] io_rx, output [13:0] tx_i, output [13:0] tx_q, input [11:0] rx_i, input [11:0] rx_q, @@ -51,6 +52,17 @@ module u1plus_core wire [31:0] debug0; wire [31:0] debug1; + wire [31:0] debug_vt; + wire rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc; + assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp; + assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp; + + setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(global_reset)); + + reset_sync reset_sync(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(wb_rst)); + // ///////////////////////////////////////////////////////////////////////////////////// // GPIF Slave to Wishbone Master localparam dw = 16; @@ -67,8 +79,6 @@ module u1plus_core wire [35:0] tx_data, rx_data, tx_err_data; wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, tx_err_src_rdy, tx_err_dst_rdy; - reg [15:0] tx_frame_len; - wire [15:0] rx_frame_len; wire bus_error; wire gpif_rst = 0; @@ -94,7 +104,10 @@ module u1plus_core .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx), .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), - + + .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc), + + .test_rate(test_rate), .test_ctrl(test_ctrl), .debug0(debug0), .debug1(debug1)); wire rx_sof = rx_data[32]; @@ -123,7 +136,7 @@ module u1plus_core vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time), .overrun(), + .vita_time(vita_time), .overrun(rx_overrun_dsp), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy), .debug_rx(vrc_debug)); @@ -158,8 +171,8 @@ module u1plus_core .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), .dac_a(tx_i_int),.dac_b(tx_q_int), - .underrun(), .run(run_tx), - .debug()); + .underrun(tx_underrun_dsp), .run(run_tx), + .debug(debug_vt)); assign tx_i = tx_i_int[15:2]; assign tx_q = tx_q_int[15:2]; @@ -275,7 +288,6 @@ module u1plus_core (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : (s0_adr[6:0] == REG_TEST) ? reg_test : - (s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len : (s0_adr[6:0] == REG_COMPAT) ? { 8'd0, COMPAT_NUM } : 16'hBEEF; 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