diff options
| -rw-r--r-- | usrp2/coregen/fifo_generator_ug175.pdf | bin | 1069823 -> 2895895 bytes | |||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo | 12 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt | 6 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt | 22 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl | 8 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo | 12 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt | 101 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt | 6 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt | 22 | ||||
| -rw-r--r-- | usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl | 8 | 
10 files changed, 60 insertions, 137 deletions
| diff --git a/usrp2/coregen/fifo_generator_ug175.pdf b/usrp2/coregen/fifo_generator_ug175.pdfBinary files differ index 2c3e3c200..5fba6029c 100644 --- a/usrp2/coregen/fifo_generator_ug175.pdf +++ b/usrp2/coregen/fifo_generator_ug175.pdf diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo index cd949ccaa..c962fddfa 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.veo @@ -23,7 +23,7 @@  *     appliances, devices, or systems. Use in such applications are            *  *     expressly prohibited.                                                    *  *                                                                              * -*     (c) Copyright 1995-2007 Xilinx, Inc.                                     * +*     (c) Copyright 1995-2009 Xilinx, Inc.                                     *  *     All rights reserved.                                                     *  *******************************************************************************/  // The following must be inserted into your Verilog file for this @@ -32,16 +32,16 @@  //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG  fifo_xlnx_512x36_2clk_18to36 YourInstanceName ( -	.din(din), // Bus [17 : 0]  -	.rd_clk(rd_clk), -	.rd_en(rd_en),  	.rst(rst),  	.wr_clk(wr_clk), +	.rd_clk(rd_clk), +	.din(din), // Bus [17 : 0]   	.wr_en(wr_en), -	.almost_full(almost_full), +	.rd_en(rd_en),  	.dout(dout), // Bus [35 : 0]  +	.full(full),  	.empty(empty), -	.full(full)); +	.prog_full(prog_full));  // INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt index 18ba3e664..2f8d522f6 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_flist.txt @@ -1,8 +1,12 @@  # Output products list for <fifo_xlnx_512x36_2clk_18to36> +_xmsgs/pn_parser.xmsgs +fifo_generator_ug175.pdf +fifo_xlnx_512x36_2clk_18to36.gise  fifo_xlnx_512x36_2clk_18to36.ngc  fifo_xlnx_512x36_2clk_18to36.v  fifo_xlnx_512x36_2clk_18to36.veo  fifo_xlnx_512x36_2clk_18to36.xco -fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_512x36_2clk_18to36.xise  fifo_xlnx_512x36_2clk_18to36_flist.txt +fifo_xlnx_512x36_2clk_18to36_readme.txt  fifo_xlnx_512x36_2clk_18to36_xmdf.tcl diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt index e0d45849d..03829e876 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_readme.txt @@ -1,5 +1,12 @@  The following files were generated for 'fifo_xlnx_512x36_2clk_18to36' in directory  -/home/matt/fpgapriv/usrp2/coregen/: +/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/ + +fifo_generator_ug175.pdf: +   Please see the core data sheet. + +fifo_xlnx_512x36_2clk_18to36.gise: +   ISE Project Navigator support file. This is a generated file and should +   not be edited directly.  fifo_xlnx_512x36_2clk_18to36.ngc:     Binary Xilinx implementation netlist file containing the information @@ -18,12 +25,9 @@ fifo_xlnx_512x36_2clk_18to36.xco:     CORE Generator input file containing the parameters used to     regenerate a core. -fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: -   Please see the core data sheet. - -fifo_xlnx_512x36_2clk_18to36_flist.txt: -   Text file listing all of the output files produced when a customized -   core was generated in the CORE Generator. +fifo_xlnx_512x36_2clk_18to36.xise: +   ISE Project Navigator support file. This is a generated file and should +   not be edited directly.  fifo_xlnx_512x36_2clk_18to36_readme.txt:     Text file indicating the files generated and how they are used. @@ -33,6 +37,10 @@ fifo_xlnx_512x36_2clk_18to36_xmdf.tcl:     how the files output by CORE Generator for the core can be integrated     into your ISE project. +fifo_xlnx_512x36_2clk_18to36_flist.txt: +   Text file listing all of the output files produced when a customized +   core was generated in the CORE Generator. +  Please see the Xilinx CORE Generator online help for further details on  generated files and how to use them. diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl index f20d53f64..9b9b1f37a 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36_xmdf.tcl @@ -36,6 +36,10 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library  utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim  incr fcount +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount +  utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36.ngc  utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc  incr fcount @@ -52,10 +56,6 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_51  utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip  incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount -  utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_18to36_xmdf.tcl  utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView  incr fcount diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo index 5c2da4b97..e93be1591 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.veo @@ -23,7 +23,7 @@  *     appliances, devices, or systems. Use in such applications are            *  *     expressly prohibited.                                                    *  *                                                                              * -*     (c) Copyright 1995-2007 Xilinx, Inc.                                     * +*     (c) Copyright 1995-2009 Xilinx, Inc.                                     *  *     All rights reserved.                                                     *  *******************************************************************************/  // The following must be inserted into your Verilog file for this @@ -32,15 +32,15 @@  //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG  fifo_xlnx_512x36_2clk_36to18 YourInstanceName ( -	.din(din), // Bus [35 : 0]  -	.rd_clk(rd_clk), -	.rd_en(rd_en),  	.rst(rst),  	.wr_clk(wr_clk), +	.rd_clk(rd_clk), +	.din(din), // Bus [35 : 0]   	.wr_en(wr_en), +	.rd_en(rd_en),  	.dout(dout), // Bus [17 : 0]  -	.empty(empty), -	.full(full)); +	.full(full), +	.empty(empty));  // INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt deleted file mode 100644 index 3abf04253..000000000 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +++ /dev/null @@ -1,101 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="yes" ?> -<document OS="lin64" product="ISE" version="10.1.03"> - -  <!--The data in this file is primarily intended for consumption by Xilinx tools. -    The structure and the elements are likely to change over the next few releases. -    This means code written to parse this file will need to be revisited each subsequent release.--> - -  <application stringID="Xst" timeStamp="Tue Aug 10 16:09:27 2010"> -    <section stringID="XST_HDL_SYNTHESIS_REPORT"> -      <item dataType="int" stringID="XST_COUNTERS" value="2"> -        <item dataType="int" stringID="XST_10BIT_UP_COUNTER" value="1"/> -        <item dataType="int" stringID="XST_9BIT_UP_COUNTER" value="1"/> -      </item> -      <item dataType="int" stringID="XST_REGISTERS" value="29"> -        <item dataType="int" stringID="XST_1BIT_REGISTER" value="15"/> -        <item dataType="int" stringID="XST_10BIT_REGISTER" value="5"/> -        <item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/> -        <item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/> -        <item dataType="int" stringID="XST_9BIT_REGISTER" value="6"/> -      </item> -      <item dataType="int" stringID="XST_XORS" value="72"> -        <item dataType="int" stringID="XST_1BIT_XOR2" value="72"/> -      </item> -    </section> -    <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT"> -      <item dataType="int" stringID="XST_FSMS" value="1"/> -      <item dataType="int" stringID="XST_COUNTERS" value="2"> -        <item dataType="int" stringID="XST_10BIT_UP_COUNTER" value="1"/> -        <item dataType="int" stringID="XST_9BIT_UP_COUNTER" value="1"/> -      </item> -      <item dataType="int" stringID="XST_REGISTERS" value="142"> -        <item dataType="int" stringID="XST_FLIPFLOPS" value="142"/> -      </item> -      <item dataType="int" stringID="XST_XORS" value="72"> -        <item dataType="int" stringID="XST_1BIT_XOR2" value="72"/> -      </item> -    </section> -    <section stringID="XST_FINAL_REGISTER_REPORT"> -      <item dataType="int" stringID="XST_REGISTERS" value="157"> -        <item dataType="int" stringID="XST_FLIPFLOPS" value="157"/> -      </item> -    </section> -    <section stringID="XST_PARTITION_REPORT"> -      <section stringID="XST_PARTITION_IMPLEMENTATION_STATUS"> -        <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/> -      </section> -    </section> -    <section stringID="XST_FINAL_REPORT"> -      <section stringID="XST_FINAL_RESULTS"> -        <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="/tmp/_cg/fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc"/> -        <item stringID="XST_OUTPUT_FORMAT" value="NGC"/> -        <item stringID="XST_OPTIMIZATION_GOAL" value="SPEED"/> -        <item stringID="XST_KEEP_HIERARCHY" value="no"/> -      </section> -      <section stringID="XST_DESIGN_STATISTICS"> -        <item stringID="XST_IOS" value="163"/> -      </section> -      <section stringID="XST_CELL_USAGE"> -        <item dataType="int" stringID="XST_BELS" value="147"> -          <item dataType="int" stringID="XST_GND" value="1"/> -          <item dataType="int" stringID="XST_LUT1" value="19"/> -          <item dataType="int" stringID="XST_LUT2" value="27"/> -          <item dataType="int" stringID="XST_LUT2L" value="2"/> -          <item dataType="int" stringID="XST_LUT3" value="9"/> -          <item dataType="int" stringID="XST_LUT3L" value="2"/> -          <item dataType="int" stringID="XST_LUT4" value="28"/> -          <item dataType="int" stringID="XST_LUT4L" value="2"/> -          <item dataType="int" stringID="XST_MUXCY" value="37"/> -          <item dataType="int" stringID="XST_VCC" value="1"/> -          <item dataType="int" stringID="XST_XORCY" value="19"/> -        </item> -        <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="157"> -          <item dataType="int" stringID="XST_FD" value="4"/> -          <item dataType="int" stringID="XST_FDC" value="78"/> -          <item dataType="int" stringID="XST_FDCE" value="62"/> -          <item dataType="int" stringID="XST_FDP" value="8"/> -          <item dataType="int" stringID="XST_FDPE" value="5"/> -        </item> -        <item dataType="int" stringID="XST_RAMS" value="1"></item> -      </section> -    </section> -    <section stringID="XST_DEVICE_UTILIZATION_SUMMARY"> -      <item stringID="XST_SELECTED_DEVICE" value="3s2000fg456-5"/> -      <item AVAILABLE="20480" dataType="int" stringID="XST_NUMBER_OF_SLICES" value="106"/> -      <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="157"/> -      <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="89"/> -      <item dataType="int" stringID="XST_NUMBER_OF_IOS" value="163"/> -      <item AVAILABLE="333" dataType="int" stringID="XST_NUMBER_OF_BONDED_IOBS" value="0"/> -      <item AVAILABLE="40" dataType="int" stringID="XST_NUMBER_OF_BRAMS" value="1"/> -    </section> -    <section stringID="XST_PARTITION_RESOURCE_SUMMARY"> -      <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/> -    </section> -    <section stringID="XST_ERRORS_STATISTICS"> -      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/> -      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="136"/> -      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="16"/> -    </section> -  </application> - -</document> diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt index aadac46c0..54c85b15e 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_flist.txt @@ -1,8 +1,12 @@  # Output products list for <fifo_xlnx_512x36_2clk_36to18> +_xmsgs/pn_parser.xmsgs +fifo_generator_ug175.pdf +fifo_xlnx_512x36_2clk_36to18.gise  fifo_xlnx_512x36_2clk_36to18.ngc  fifo_xlnx_512x36_2clk_36to18.v  fifo_xlnx_512x36_2clk_36to18.veo  fifo_xlnx_512x36_2clk_36to18.xco -fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_512x36_2clk_36to18.xise  fifo_xlnx_512x36_2clk_36to18_flist.txt +fifo_xlnx_512x36_2clk_36to18_readme.txt  fifo_xlnx_512x36_2clk_36to18_xmdf.tcl diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt index 568c757ec..3efc586bf 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_readme.txt @@ -1,5 +1,12 @@  The following files were generated for 'fifo_xlnx_512x36_2clk_36to18' in directory  -/home/matt/fpgapriv/usrp2/coregen/: +/home/ianb/ettus/sram_fifo/fpgapriv/usrp2/coregen/ + +fifo_generator_ug175.pdf: +   Please see the core data sheet. + +fifo_xlnx_512x36_2clk_36to18.gise: +   ISE Project Navigator support file. This is a generated file and should +   not be edited directly.  fifo_xlnx_512x36_2clk_36to18.ngc:     Binary Xilinx implementation netlist file containing the information @@ -18,12 +25,9 @@ fifo_xlnx_512x36_2clk_36to18.xco:     CORE Generator input file containing the parameters used to     regenerate a core. -fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: -   Please see the core data sheet. - -fifo_xlnx_512x36_2clk_36to18_flist.txt: -   Text file listing all of the output files produced when a customized -   core was generated in the CORE Generator. +fifo_xlnx_512x36_2clk_36to18.xise: +   ISE Project Navigator support file. This is a generated file and should +   not be edited directly.  fifo_xlnx_512x36_2clk_36to18_readme.txt:     Text file indicating the files generated and how they are used. @@ -33,6 +37,10 @@ fifo_xlnx_512x36_2clk_36to18_xmdf.tcl:     how the files output by CORE Generator for the core can be integrated     into your ISE project. +fifo_xlnx_512x36_2clk_36to18_flist.txt: +   Text file listing all of the output files produced when a customized +   core was generated in the CORE Generator. +  Please see the Xilinx CORE Generator online help for further details on  generated files and how to use them. diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl index 09248b321..5161c1826 100644 --- a/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl +++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18_xmdf.tcl @@ -36,6 +36,10 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library  utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim  incr fcount +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount +  utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18.ngc  utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc  incr fcount @@ -52,10 +56,6 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_51  utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip  incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18_fifo_generator_v4_3_xst_1.ngc_xst.xrpt -utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView -incr fcount -  utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_36to18_xmdf.tcl  utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView  incr fcount | 
