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| author | michael-west <michael.west@ettus.com> | 2014-03-15 08:42:05 -0700 |
|---|---|---|
| committer | michael-west <michael.west@ettus.com> | 2014-03-15 08:42:05 -0700 |
| commit | 9126069560de0a462f58596055dad15b35693dce (patch) | |
| tree | 09b7e56693961fbc1a0ed725acd03c9f3c62c35b /host/lib/usrp/x300/x300_impl.hpp | |
| parent | fe90695e96630864e376e3becee30cb1f01083b8 (diff) | |
| download | uhd-9126069560de0a462f58596055dad15b35693dce.tar.gz uhd-9126069560de0a462f58596055dad15b35693dce.tar.bz2 uhd-9126069560de0a462f58596055dad15b35693dce.zip | |
Addressed comments from review.
- Fixed typos.
- Renamed reset() to reset_clocks().
- Created wait_for_ref_locked() function.
Diffstat (limited to 'host/lib/usrp/x300/x300_impl.hpp')
| -rw-r--r-- | host/lib/usrp/x300/x300_impl.hpp | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/host/lib/usrp/x300/x300_impl.hpp b/host/lib/usrp/x300/x300_impl.hpp index b64f9ad01..059c1265c 100644 --- a/host/lib/usrp/x300/x300_impl.hpp +++ b/host/lib/usrp/x300/x300_impl.hpp @@ -204,11 +204,11 @@ private: gpio_core_200::sptr fp_gpio; //clock control register bits - int clock_control_regs__clock_source; - int clock_control_regs__pps_select; - int clock_control_regs__pps_out_enb; - int clock_control_regs__tcxo_enb; - int clock_control_regs__gpsdo_pwr; + int clock_control_regs_clock_source; + int clock_control_regs_pps_select; + int clock_control_regs_pps_out_enb; + int clock_control_regs_tcxo_enb; + int clock_control_regs_gpsdo_pwr; //which FPGA image is loaded std::string loaded_fpga_image; @@ -302,6 +302,7 @@ private: void update_time_source(mboard_members_t&, const std::string &); uhd::sensor_value_t get_ref_locked(uhd::wb_iface::sptr); + void wait_for_ref_locked(uhd::wb_iface::sptr, double timeout = 0.0); bool is_pps_present(uhd::wb_iface::sptr); void set_db_eeprom(uhd::i2c_iface::sptr i2c, const size_t, const uhd::usrp::dboard_eeprom_t &); |
