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authorJosh Blum <josh@joshknows.com>2011-10-26 19:31:35 -0700
committerJosh Blum <josh@joshknows.com>2011-11-03 21:00:07 -0700
commit69adaee902c5f409ebd7844667a0c253d7a06c6a (patch)
treef0d8a7d8ca940ecc0196063136e737888bf28fbe /host/lib/usrp/usrp2/usrp2_regs.hpp
parent07fb8d2b82c59ddaf7722b12db8c1387011fb34b (diff)
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usrp2: reg map change for GPIO core
Diffstat (limited to 'host/lib/usrp/usrp2/usrp2_regs.hpp')
-rw-r--r--host/lib/usrp/usrp2/usrp2_regs.hpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp
index 8839997f1..179a930c6 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.hpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.hpp
@@ -50,6 +50,7 @@
#define SR_TX_CTRL 144 // 6
#define SR_TX_DSP 160 // 5
+#define SR_GPIO 184
#define SR_UDP_SM 192 // 64
#define U2_REG_SR_ADDR(sr) (SETTING_REGS_BASE + (4 * (sr)))
@@ -95,6 +96,7 @@
// Readback regs
////////////////////////////////////////////////
#define U2_REG_STATUS READBACK_BASE + 4*8
+#define U2_REG_GPIO_RB READBACK_BASE + 4*9
#define U2_REG_TIME64_SECS_RB_IMM READBACK_BASE + 4*10
#define U2_REG_TIME64_TICKS_RB_IMM READBACK_BASE + 4*11
#define U2_REG_COMPAT_NUM_RB READBACK_BASE + 4*12