Merge branch 'next'

4 files changed, 54 insertions, 47 deletions

diff --git a/host/lib/usrp/e100/e100_impl.cpp b/host/lib/usrp/e100/e100_impl.cpp
index f58138ae6..a01ce4a7b 100644
--- a/host/lib/usrp/e100/e100_impl.cpp
+++ b/host/lib/usrp/e100/e100_impl.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010-2011 Ettus Research LLC
+// Copyright 2010-2012 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -326,10 +326,10 @@ e100_impl::e100_impl(const uhd::device_addr_t &device_addr){
     // create time control objects
     ////////////////////////////////////////////////////////////////////
     time64_core_200::readback_bases_type time64_rb_bases;
-    time64_rb_bases.rb_secs_now = E100_REG_RB_TIME_NOW_SECS;
-    time64_rb_bases.rb_ticks_now = E100_REG_RB_TIME_NOW_TICKS;
-    time64_rb_bases.rb_secs_pps = E100_REG_RB_TIME_PPS_SECS;
-    time64_rb_bases.rb_ticks_pps = E100_REG_RB_TIME_PPS_TICKS;
+    time64_rb_bases.rb_hi_now = E100_REG_RB_TIME_NOW_HI;
+    time64_rb_bases.rb_lo_now = E100_REG_RB_TIME_NOW_LO;
+    time64_rb_bases.rb_hi_pps = E100_REG_RB_TIME_PPS_HI;
+    time64_rb_bases.rb_lo_pps = E100_REG_RB_TIME_PPS_LO;
     _time64 = time64_core_200::make(
         _fpga_ctrl, E100_REG_SR_ADDR(UE_SR_TIME64), time64_rb_bases
     );
@@ -353,6 +353,13 @@ e100_impl::e100_impl(const uhd::device_addr_t &device_addr){
     _tree->create<std::vector<std::string> >(mb_path / "clock_source/options").set(clock_sources);
 
     ////////////////////////////////////////////////////////////////////
+    // create user-defined control objects
+    ////////////////////////////////////////////////////////////////////
+    _user = user_settings_core_200::make(_fpga_ctrl, E100_REG_SR_ADDR(UE_SR_USER_REGS));
+    _tree->create<user_settings_core_200::user_reg_t>(mb_path / "user/regs")
+        .subscribe(boost::bind(&user_settings_core_200::set_reg, _user, _1));
+
+    ////////////////////////////////////////////////////////////////////
     // create dboard control objects
     ////////////////////////////////////////////////////////////////////
 
diff --git a/host/lib/usrp/e100/e100_impl.hpp b/host/lib/usrp/e100/e100_impl.hpp
index 2ea890375..1d36cb2ac 100644
--- a/host/lib/usrp/e100/e100_impl.hpp
+++ b/host/lib/usrp/e100/e100_impl.hpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010-2011 Ettus Research LLC
+// Copyright 2010-2012 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -25,6 +25,7 @@
 #include "rx_dsp_core_200.hpp"
 #include "tx_dsp_core_200.hpp"
 #include "time64_core_200.hpp"
+#include "user_settings_core_200.hpp"
 #include <uhd/device.hpp>
 #include <uhd/property_tree.hpp>
 #include <uhd/utils/pimpl.hpp>
@@ -48,7 +49,7 @@ static const double          E100_RX_LINK_RATE_BPS = 166e6/3/2*2;
 static const double          E100_TX_LINK_RATE_BPS = 166e6/3/1*2;
 static const std::string     E100_I2C_DEV_NODE = "/dev/i2c-3";
 static const std::string     E100_UART_DEV_NODE = "/dev/ttyO0";
-static const boost::uint16_t E100_FPGA_COMPAT_NUM = 0x08;
+static const boost::uint16_t E100_FPGA_COMPAT_NUM = 0x09;
 static const boost::uint32_t E100_RX_SID_BASE = 2;
 static const boost::uint32_t E100_TX_ASYNC_SID = 1;
 static const double          E100_DEFAULT_CLOCK_RATE = 64e6;
@@ -92,6 +93,7 @@ private:
     std::vector<rx_dsp_core_200::sptr> _rx_dsps;
     tx_dsp_core_200::sptr _tx_dsp;
     time64_core_200::sptr _time64;
+    user_settings_core_200::sptr _user;
     e100_clock_ctrl::sptr _clock_ctrl;
     e100_codec_ctrl::sptr _codec_ctrl;
     e100_ctrl::sptr _fpga_ctrl;
diff --git a/host/lib/usrp/e100/e100_regs.hpp b/host/lib/usrp/e100/e100_regs.hpp
index f24f5895b..75be2cfbe 100644
--- a/host/lib/usrp/e100/e100_regs.hpp
+++ b/host/lib/usrp/e100/e100_regs.hpp
@@ -1,4 +1,19 @@
-
+//
+// Copyright 2010-2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
 
 ////////////////////////////////////////////////////////////////
 //
@@ -71,10 +86,10 @@
 
 #define E100_REG_RB_MUX_32_BASE  E100_REG_SLAVE(7)
 
-#define E100_REG_RB_TIME_NOW_SECS   E100_REG_RB_MUX_32_BASE + 0
-#define E100_REG_RB_TIME_NOW_TICKS  E100_REG_RB_MUX_32_BASE + 4
-#define E100_REG_RB_TIME_PPS_SECS   E100_REG_RB_MUX_32_BASE + 8
-#define E100_REG_RB_TIME_PPS_TICKS  E100_REG_RB_MUX_32_BASE + 12
+#define E100_REG_RB_TIME_NOW_HI     E100_REG_RB_MUX_32_BASE + 0
+#define E100_REG_RB_TIME_NOW_LO     E100_REG_RB_MUX_32_BASE + 4
+#define E100_REG_RB_TIME_PPS_HI     E100_REG_RB_MUX_32_BASE + 8
+#define E100_REG_RB_TIME_PPS_LO     E100_REG_RB_MUX_32_BASE + 12
 #define E100_REG_RB_MISC_TEST32     E100_REG_RB_MUX_32_BASE + 16
 #define E100_REG_RB_ERR_STATUS      E100_REG_RB_MUX_32_BASE + 20
 #define E100_REG_RB_COMPAT          E100_REG_RB_MUX_32_BASE + 24
@@ -101,9 +116,9 @@
 #define UE_SR_TX_FRONT 54      // 5 regs (+0 to +4)
 
 #define UE_SR_REG_TEST32 60    // 1 reg
-#define UE_SR_CLEAR_RX_FIFO 61 // 1 reg
-#define UE_SR_CLEAR_TX_FIFO 62 // 1 reg
+#define UE_SR_CLEAR_FIFO 61    // 1 reg
 #define UE_SR_GLOBAL_RESET 63  // 1 reg
+#define UE_SR_USER_REGS 64     // 2 regs
 
 #define UE_SR_GPIO 128
 
@@ -115,8 +130,7 @@
 /////////////////////////////////////////////////
 // Magic reset regs
 ////////////////////////////////////////////////
-#define E100_REG_CLEAR_RX           E100_REG_SR_ADDR(UE_SR_CLEAR_RX_FIFO)
-#define E100_REG_CLEAR_TX           E100_REG_SR_ADDR(UE_SR_CLEAR_RX_FIFO)
+#define E100_REG_CLEAR_FIFO         E100_REG_SR_ADDR(UE_SR_CLEAR_FIFO)
 #define E100_REG_GLOBAL_RESET       E100_REG_SR_ADDR(UE_SR_GLOBAL_RESET)
 
 #endif
diff --git a/host/lib/usrp/e100/io_impl.cpp b/host/lib/usrp/e100/io_impl.cpp
index 441e32a8d..e9608125f 100644
--- a/host/lib/usrp/e100/io_impl.cpp
+++ b/host/lib/usrp/e100/io_impl.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010-2011 Ettus Research LLC
+// Copyright 2010-2012 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -17,6 +17,7 @@
 
 #include "recv_packet_demuxer.hpp"
 #include "validate_subdev_spec.hpp"
+#include "async_packet_handler.hpp"
 #include "../../transport/super_recv_packet_handler.hpp"
 #include "../../transport/super_send_packet_handler.hpp"
 #include <linux/usrp_e.h> //ioctl structures and constants
@@ -50,7 +51,7 @@ using namespace uhd::transport;
  **********************************************************************/
 struct e100_impl::io_impl{
     io_impl(void):
-        false_alarm(0), async_msg_fifo(100/*messages deep*/)
+        false_alarm(0), async_msg_fifo(1000/*messages deep*/)
     { /* NOP */ }
 
     double tick_rate; //set by update tick rate method
@@ -123,28 +124,13 @@ void e100_impl::io_impl::handle_irq(void){
 
         //fill in the async metadata
         async_metadata_t metadata;
-        metadata.channel = 0;
-        metadata.has_time_spec = if_packet_info.has_tsi and if_packet_info.has_tsf;
-        metadata.time_spec = time_spec_t(
-            time_t(if_packet_info.tsi), long(if_packet_info.tsf), tick_rate
-        );
-        metadata.event_code = async_metadata_t::event_code_t(sph::get_context_code(data.buf, if_packet_info));
+        load_metadata_from_buff(uhd::wtohx<boost::uint32_t>, metadata, if_packet_info, data.buf, tick_rate);
 
         //push the message onto the queue
         async_msg_fifo.push_with_pop_on_full(metadata);
 
         //print some fastpath messages
-        if (metadata.event_code &
-            ( async_metadata_t::EVENT_CODE_UNDERFLOW
-            | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET)
-        ) UHD_MSG(fastpath) << "U";
-        else if (metadata.event_code &
-            ( async_metadata_t::EVENT_CODE_SEQ_ERROR
-            | async_metadata_t::EVENT_CODE_SEQ_ERROR_IN_BURST)
-        ) UHD_MSG(fastpath) << "S";
-        else if (metadata.event_code &
-            async_metadata_t::EVENT_CODE_TIME_ERROR
-        ) UHD_MSG(fastpath) << "L";
+        standard_async_msg_prints(metadata);
     }
 
     //prepare for the next round
@@ -164,9 +150,8 @@ void e100_impl::io_init(void){
     _io_impl->demuxer = recv_packet_demuxer::make(_data_transport, _rx_dsps.size(), E100_RX_SID_BASE);
     _io_impl->iface = _fpga_ctrl;
 
-    //clear state machines
-    _fpga_ctrl->poke32(E100_REG_CLEAR_RX, 0);
-    _fpga_ctrl->poke32(E100_REG_CLEAR_TX, 0);
+    //clear fifo state machines
+    _fpga_ctrl->poke32(E100_REG_CLEAR_FIFO, 0);
 
     //allocate streamer weak ptrs containers
     _rx_streamers.resize(_rx_dsps.size());
@@ -217,6 +202,8 @@ void e100_impl::update_tx_samp_rate(const size_t dspno, const double rate){
     if (my_streamer.get() == NULL) return;
 
     my_streamer->set_samp_rate(rate);
+    const double adj = _tx_dsp->get_scaling_adjustment();
+    my_streamer->set_scale_factor(adj);
 }
 
 void e100_impl::update_rates(void){
@@ -278,13 +265,13 @@ rx_streamer::sptr e100_impl::get_rx_stream(const uhd::stream_args_t &args_){
     //setup defaults for unspecified values
     args.otw_format = args.otw_format.empty()? "sc16" : args.otw_format;
     args.channels = args.channels.empty()? std::vector<size_t>(1, 0) : args.channels;
-    const unsigned sc8_scalar = unsigned(args.args.cast<double>("scalar", 0x400));
 
     //calculate packet size
     static const size_t hdr_size = 0
         + vrt::max_if_hdr_words32*sizeof(boost::uint32_t)
         + sizeof(vrt::if_packet_info_t().tlr) //forced to have trailer
         - sizeof(vrt::if_packet_info_t().cid) //no class id ever used
+        - sizeof(vrt::if_packet_info_t().tsi) //no int time ever used
     ;
     const size_t bpp = _data_transport->get_recv_frame_size() - hdr_size;
     const size_t bpi = convert::get_bytes_per_item(args.otw_format);
@@ -309,8 +296,7 @@ rx_streamer::sptr e100_impl::get_rx_stream(const uhd::stream_args_t &args_){
     for (size_t chan_i = 0; chan_i < args.channels.size(); chan_i++){
         const size_t dsp = args.channels[chan_i];
         _rx_dsps[dsp]->set_nsamps_per_packet(spp); //seems to be a good place to set this
-        if (not args.args.has_key("noclear")) _rx_dsps[dsp]->clear();
-        _rx_dsps[dsp]->set_format(args.otw_format, sc8_scalar);
+        _rx_dsps[dsp]->setup(args);
         my_streamer->set_xport_chan_get_buff(chan_i, boost::bind(
             &recv_packet_demuxer::get_recv_buff, _io_impl->demuxer, dsp, _1
         ), true /*flush*/);
@@ -336,14 +322,13 @@ tx_streamer::sptr e100_impl::get_tx_stream(const uhd::stream_args_t &args_){
     args.otw_format = args.otw_format.empty()? "sc16" : args.otw_format;
     args.channels = args.channels.empty()? std::vector<size_t>(1, 0) : args.channels;
 
-    if (args.otw_format != "sc16"){
-        throw uhd::value_error("USRP TX cannot handle requested wire format: " + args.otw_format);
-    }
-
     //calculate packet size
     static const size_t hdr_size = 0
         + vrt::max_if_hdr_words32*sizeof(boost::uint32_t)
+        + sizeof(vrt::if_packet_info_t().tlr) //forced to have trailer
+        - sizeof(vrt::if_packet_info_t().sid) //no stream id ever used
         - sizeof(vrt::if_packet_info_t().cid) //no class id ever used
+        - sizeof(vrt::if_packet_info_t().tsi) //no int time ever used
     ;
     static const size_t bpp = _data_transport->get_send_frame_size() - hdr_size;
     const size_t spp = bpp/convert::get_bytes_per_item(args.otw_format);
@@ -367,8 +352,7 @@ tx_streamer::sptr e100_impl::get_tx_stream(const uhd::stream_args_t &args_){
     for (size_t chan_i = 0; chan_i < args.channels.size(); chan_i++){
         const size_t dsp = args.channels[chan_i];
         UHD_ASSERT_THROW(dsp == 0); //always 0
-        if (not args.args.has_key("noclear")) _tx_dsp->clear();
-        if (args.args.has_key("underflow_policy")) _tx_dsp->set_underflow_policy(args.args["underflow_policy"]);
+        _tx_dsp->setup(args);
         my_streamer->set_xport_chan_get_buff(chan_i, boost::bind(
             &zero_copy_if::get_send_buff, _data_transport, _1
         ));