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| author | Andrew Moch <Andrew.Moch@ni.com> | 2020-03-11 19:39:06 +0100 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-03-20 10:34:59 -0500 |
| commit | b296b26053d4437b8ae97e3df415a3d041b7b51e (patch) | |
| tree | fa34231aec17809dff523d81aa513a7f990069a5 /host/lib/deps/flatbuffers | |
| parent | 07b85b6dcc6e84f42da3579b65692a3d4ba04e38 (diff) | |
| download | uhd-b296b26053d4437b8ae97e3df415a3d041b7b51e.tar.gz uhd-b296b26053d4437b8ae97e3df415a3d041b7b51e.tar.bz2 uhd-b296b26053d4437b8ae97e3df415a3d041b7b51e.zip | |
fpga: tools: Add modelsim to make sim targets
This adds a simulation make target that allows you to run ModelSim
natively rather than through Vivado.
Adds or modifies the following simulation make targets:
make vlint - Brake up compilation to Verilog/SystemVerilog/VHDL
make modelsim - Depends on make vlint and invokes modelsim
Adds the following variables:
MODELSIM_ARGS - Added to invocation of ModelSim
SVLOG_ARGS - Added to SystemVerilog invocation of vlog
VLOG_ARGS - Added to Verilog invocation of vlog
VHDL_ARGS - Added to VHDL invocation of vcom
Diffstat (limited to 'host/lib/deps/flatbuffers')
0 files changed, 0 insertions, 0 deletions