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| author | Matt Ettus <matt@ettus.com> | 2010-05-04 12:30:56 -0700 |
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| committer | Matt Ettus <matt@ettus.com> | 2010-05-04 12:30:56 -0700 |
| commit | 031becd1f05f0fbcab6a4f2be353292cd667a88f (patch) | |
| tree | 33fd5a9c2580615e98baa6729671f07bdecac4e8 /fpga | |
| parent | b30cbe85e8537de6a94e481a57033b5e57a73e12 (diff) | |
| download | uhd-031becd1f05f0fbcab6a4f2be353292cd667a88f.tar.gz uhd-031becd1f05f0fbcab6a4f2be353292cd667a88f.tar.bz2 uhd-031becd1f05f0fbcab6a4f2be353292cd667a88f.zip | |
add timing constraints. Just have main clock signal at 64 MHz for now.
Diffstat (limited to 'fpga')
0 files changed, 0 insertions, 0 deletions