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authorBen Hilburn <ben.hilburn@ettus.com>2014-02-14 12:05:07 -0800
committerBen Hilburn <ben.hilburn@ettus.com>2014-02-14 12:05:07 -0800
commitff1546f8137f7f92bb250f685561b0c34cc0e053 (patch)
tree7fa6fd05c8828df256a1b20e2935bd3ba9899e2c /fpga/usrp3/top/x300/ddr3.ucf
parent4f691d88123784c2b405816925f1a1aef69d18c1 (diff)
downloaduhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.tar.gz
uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.tar.bz2
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Pushing the bulk of UHD-3.7.0 code.
Diffstat (limited to 'fpga/usrp3/top/x300/ddr3.ucf')
-rw-r--r--fpga/usrp3/top/x300/ddr3.ucf176
1 files changed, 176 insertions, 0 deletions
diff --git a/fpga/usrp3/top/x300/ddr3.ucf b/fpga/usrp3/top/x300/ddr3.ucf
new file mode 100644
index 000000000..7f83efacf
--- /dev/null
+++ b/fpga/usrp3/top/x300/ddr3.ucf
@@ -0,0 +1,176 @@
+##################################################################################################
+##
+## Xilinx, Inc. 2010 www.xilinx.com
+## Thu Jan 24 15:58:24 2013
+## Generated by MIG Version 1.8
+##
+##################################################################################################
+## File name : ddr3_32bit.ucf
+## Details : Constraints file
+## FPGA Family: KINTEX7
+## FPGA Part: XC7K410T-FFG900
+## Speedgrade: -2
+## Design Entry: VERILOG
+## Frequency: 500 MHz
+## Time Period: 2000 ps
+##################################################################################################
+
+##################################################################################################
+## Controller 0
+## Memory Device: DDR3_SDRAM->Components->MT41J256m16XX-125
+## Data Width: 32
+## Time Period: 2000
+## Data Mask: 1
+##################################################################################################
+
+NET "sys_clk_i" TNM_NET = TNM_sys_clk;
+TIMESPEC "TS_sys_clk" = PERIOD "TNM_sys_clk" 10 ns;
+
+#NET "clk_ref_i" TNM_NET = TNM_clk_ref;
+#TIMESPEC "TS_clk_ref" = PERIOD "TNM_clk_ref" 5 ns ;
+
+# Note: the following CLOCK_DEDICATED_ROUTE constraint will cause a warning in place similar
+# to the following:
+# WARNING:Place:1402 - A clock IOB / PLL clock component pair have been found that are not
+# placed at an optimal clock IOB / PLL site pair.
+# This warning can be ignored. See the Users Guide for more information.
+
+NET "sys_clk_i" CLOCK_DEDICATED_ROUTE = BACKBONE;
+PIN "*/u_ddr3_infrastructure/plle2_i.CLKIN1" CLOCK_DEDICATED_ROUTE = BACKBONE;
+
+
+############## NET - IOSTANDARD ##################
+
+NET "ddr3_dq[0]" LOC = "AD3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L1N_T0_34
+NET "ddr3_dq[1]" LOC = "AC2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L2P_T0_34
+NET "ddr3_dq[2]" LOC = "AC1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L2N_T0_34
+NET "ddr3_dq[3]" LOC = "AC5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L4P_T0_34
+NET "ddr3_dq[4]" LOC = "AC4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L4N_T0_34
+NET "ddr3_dq[5]" LOC = "AD6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L5P_T0_34
+NET "ddr3_dq[6]" LOC = "AE6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L5N_T0_34
+NET "ddr3_dq[7]" LOC = "AC7" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L6P_T0_34
+NET "ddr3_dq[8]" LOC = "AF2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L7N_T1_34
+NET "ddr3_dq[9]" LOC = "AE1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L8P_T1_34
+NET "ddr3_dq[10]" LOC = "AF1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L8N_T1_34
+NET "ddr3_dq[11]" LOC = "AE4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L10P_T1_34
+NET "ddr3_dq[12]" LOC = "AE3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L10N_T1_34
+NET "ddr3_dq[13]" LOC = "AE5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L11P_T1_SRCC_34
+NET "ddr3_dq[14]" LOC = "AF5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L11N_T1_SRCC_34
+NET "ddr3_dq[15]" LOC = "AF6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L12P_T1_MRCC_34
+NET "ddr3_dq[16]" LOC = "AJ4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L13N_T2_MRCC_34
+NET "ddr3_dq[17]" LOC = "AH6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L14P_T2_SRCC_34
+NET "ddr3_dq[18]" LOC = "AH5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L14N_T2_SRCC_34
+NET "ddr3_dq[19]" LOC = "AH2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L16P_T2_34
+NET "ddr3_dq[20]" LOC = "AJ2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L16N_T2_34
+NET "ddr3_dq[21]" LOC = "AJ1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L17P_T2_34
+NET "ddr3_dq[22]" LOC = "AK1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L17N_T2_34
+NET "ddr3_dq[23]" LOC = "AJ3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L18P_T2_34
+NET "ddr3_dq[24]" LOC = "AF7" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L20P_T3_34
+NET "ddr3_dq[25]" LOC = "AG7" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L20N_T3_34
+NET "ddr3_dq[26]" LOC = "AJ6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L22P_T3_34
+NET "ddr3_dq[27]" LOC = "AK6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L22N_T3_34
+NET "ddr3_dq[28]" LOC = "AJ8" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L23P_T3_34
+NET "ddr3_dq[29]" LOC = "AK8" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L23N_T3_34
+NET "ddr3_dq[30]" LOC = "AK5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L24P_T3_34
+NET "ddr3_dq[31]" LOC = "AK4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L24N_T3_34
+NET "ddr3_addr[14]" LOC = "AA12" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L1P_T0_33
+NET "ddr3_addr[13]" LOC = "AB12" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L1N_T0_33
+NET "ddr3_addr[12]" LOC = "AA8" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L2P_T0_33
+NET "ddr3_addr[11]" LOC = "AB8" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L2N_T0_33
+NET "ddr3_addr[10]" LOC = "Y11" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L4P_T0_33
+NET "ddr3_addr[9]" LOC = "Y10" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L4N_T0_33
+NET "ddr3_addr[8]" LOC = "AA11" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L5P_T0_33
+NET "ddr3_addr[7]" LOC = "AA10" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L5N_T0_33
+NET "ddr3_addr[6]" LOC = "AA13" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L6P_T0_33
+NET "ddr3_addr[5]" LOC = "AB13" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L6N_T0_VREF_33
+NET "ddr3_addr[4]" LOC = "AB10" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L7P_T1_33
+NET "ddr3_addr[3]" LOC = "AC10" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L7N_T1_33
+NET "ddr3_addr[2]" LOC = "AD8" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L8P_T1_33
+NET "ddr3_addr[1]" LOC = "AE8" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L8N_T1_33
+NET "ddr3_addr[0]" LOC = "AC12" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L9P_T1_DQS_33
+NET "ddr3_ba[2]" LOC = "AC11" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L9N_T1_DQS_33
+NET "ddr3_ba[1]" LOC = "AD9" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L10P_T1_33
+NET "ddr3_ba[0]" LOC = "AE9" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L10N_T1_33
+NET "ddr3_ras_n" LOC = "AE11" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L11P_T1_SRCC_33
+NET "ddr3_cas_n" LOC = "AF11" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L11N_T1_SRCC_33
+NET "ddr3_we_n" LOC = "AD12" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L12P_T1_MRCC_33
+NET "ddr3_reset_n" LOC = "AG5" | IOSTANDARD = LVCMOS15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L12N_T1_MRCC_34
+NET "ddr3_cke[0]" LOC = "AJ9" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L15P_T2_DQS_33
+NET "ddr3_odt[0]" LOC = "AK9" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L15N_T2_DQS_33
+NET "ddr3_cs_n[0]" LOC = "AD11" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L12N_T1_MRCC_33
+NET "ddr3_dm[0]" LOC = "AD4" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L1P_T0_34
+NET "ddr3_dm[1]" LOC = "AF3" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L7P_T1_34
+NET "ddr3_dm[2]" LOC = "AH4" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L13P_T2_MRCC_34
+NET "ddr3_dm[3]" LOC = "AF8" | IOSTANDARD = SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L19P_T3_34
+NET "sys_clk_i" LOC = "AE10" | IOSTANDARD = LVCMOS15 | VCCAUX_IO = NORMAL ; # Manual change that wasn't allowed by MIG v1.8
+#NET "sys_clk_i" LOC = "AD17" | IOSTANDARD = LVCMOS18 | VCCAUX_IO = DONTCARE ; # Pad function: IO_L14P_T2_SRCC_32
+NET "ddr3_dqs_p[0]" LOC = "AD2" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L3P_T0_DQS_34
+NET "ddr3_dqs_n[0]" LOC = "AD1" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L3N_T0_DQS_34
+NET "ddr3_dqs_p[1]" LOC = "AG4" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L9P_T1_DQS_34
+NET "ddr3_dqs_n[1]" LOC = "AG3" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L9N_T1_DQS_34
+NET "ddr3_dqs_p[2]" LOC = "AG2" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L15P_T2_DQS_34
+NET "ddr3_dqs_n[2]" LOC = "AH1" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L15N_T2_DQS_34
+NET "ddr3_dqs_p[3]" LOC = "AH7" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L21P_T3_DQS_34
+NET "ddr3_dqs_n[3]" LOC = "AJ7" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L21N_T3_DQS_34
+NET "ddr3_ck_p[0]" LOC = "AB9" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L3P_T0_DQS_33
+NET "ddr3_ck_n[0]" LOC = "AC9" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = NORMAL | SLEW = FAST ; # Pad function: IO_L3N_T0_DQS_33
+
+
+
+INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y7;
+INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y6;
+INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y5;
+INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y11;
+INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y10;
+INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y9;
+INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out" LOC=PHASER_OUT_PHY_X1Y8;
+
+## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y7;
+## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y6;
+## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y5;
+INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y11;
+INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y10;
+INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y9;
+INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y8;
+
+
+
+INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo" LOC=OUT_FIFO_X1Y7;
+INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y6;
+INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y5;
+INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo" LOC=OUT_FIFO_X1Y11;
+INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y10;
+INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y9;
+INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo" LOC=OUT_FIFO_X1Y8;
+
+INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y11;
+INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y10;
+INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y9;
+INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y8;
+
+INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y1;
+INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y2;
+
+INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y1;
+INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y2;
+
+
+INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y143;
+INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y131;
+INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y119;
+INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y107;
+
+INST "*/u_ddr3_infrastructure/plle2_i" LOC=PLLE2_ADV_X1Y1;
+INST "*/u_ddr3_infrastructure/mmcm_i" LOC=MMCME2_ADV_X1Y1;
+
+
+NET "*/iserdes_clk" TNM_NET = "TNM_ISERDES_CLK";
+INST "*/mc0/mc_read_idle_r" TNM = "TNM_SOURCE_IDLE";
+INST "*/input_[?].iserdes_dq_.iserdesdq" TNM = "TNM_DEST_ISERDES";
+TIMESPEC "TS_ISERDES_CLOCK" = PERIOD "TNM_ISERDES_CLK" 2000 ps;
+TIMESPEC TS_MULTICYCLEPATH = FROM "TNM_SOURCE_IDLE" TO "TNM_DEST_ISERDES" TS_ISERDES_CLOCK*6;
+
+
+INST "*/device_temp_sync_r1*" TNM="TNM_MULTICYCLEPATH_DEVICE_TEMP_SYNC";
+TIMESPEC "TS_MULTICYCLEPATH_DEVICE_TEMP_SYNC" = TO "TNM_MULTICYCLEPATH_DEVICE_TEMP_SYNC" 20 ns DATAPATHONLY;
+ \ No newline at end of file
generated by cgit v1.2.3 (git 2.46.0) at 2025-10-31 22:59:48 +0000