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| author | Thomas Tsou <ttsou@vt.edu> | 2010-08-23 15:21:14 -0700 |
|---|---|---|
| committer | Thomas Tsou <ttsou@vt.edu> | 2010-08-23 15:21:14 -0700 |
| commit | 3f4e998bbf59dcc1c5df88ed37ca74f80a1b2e70 (patch) | |
| tree | 18189f75df2011cb19c1da286aafb233c0da8788 /fpga/usrp2/sdr_lib/add2.v | |
| parent | 4021779856d6b971fa8add5f617528158bf727a2 (diff) | |
| download | uhd-3f4e998bbf59dcc1c5df88ed37ca74f80a1b2e70.tar.gz uhd-3f4e998bbf59dcc1c5df88ed37ca74f80a1b2e70.tar.bz2 uhd-3f4e998bbf59dcc1c5df88ed37ca74f80a1b2e70.zip | |
usrp1: Remove hard coded value in clock rate property
Diffstat (limited to 'fpga/usrp2/sdr_lib/add2.v')
0 files changed, 0 insertions, 0 deletions