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| author | michael-west <michael.west@ettus.com> | 2014-05-13 16:09:13 -0700 |
|---|---|---|
| committer | michael-west <michael.west@ettus.com> | 2014-05-13 16:09:13 -0700 |
| commit | 01e5d630d9d5525b46d2814808a974084f1e13fb (patch) | |
| tree | 38158dc3c8144011917e06a0f8a719452ee4c096 /fpga/usrp2/models/cpld_model.v | |
| parent | 0e51394db05b3e66ed5f7335eff363d658b3f47c (diff) | |
| download | uhd-01e5d630d9d5525b46d2814808a974084f1e13fb.tar.gz uhd-01e5d630d9d5525b46d2814808a974084f1e13fb.tar.bz2 uhd-01e5d630d9d5525b46d2814808a974084f1e13fb.zip | |
Fix for BUG 473: UHD: DBSRX2 VCO Autoselect Failing / Wrong Frequency Range
- Corrected frequency range for DBSRX2
- Corrected register write order when changing frequency
Diffstat (limited to 'fpga/usrp2/models/cpld_model.v')
0 files changed, 0 insertions, 0 deletions