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authorJosh Blum <josh@joshknows.com>2010-04-15 11:24:41 -0700
committerJosh Blum <josh@joshknows.com>2010-04-15 11:24:41 -0700
commit3a196c5d614fbec9b1010b3082245614ba5e0dc9 (patch)
tree784f075298f5d86c9e7429ce0ff977deaf4315c8 /fpga/usrp2/control_lib/wb_ram_dist.v
parentcbf7a0916f0455743d8446a8edc0f0775e3e63ed (diff)
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Merge branch 'udp'
Diffstat (limited to 'fpga/usrp2/control_lib/wb_ram_dist.v')
-rw-r--r--fpga/usrp2/control_lib/wb_ram_dist.v33
1 files changed, 33 insertions, 0 deletions
diff --git a/fpga/usrp2/control_lib/wb_ram_dist.v b/fpga/usrp2/control_lib/wb_ram_dist.v
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+
+
+module wb_ram_dist
+ #(parameter AWIDTH=8)
+ (input clk_i,
+ input stb_i,
+ input we_i,
+ input [AWIDTH-1:0] adr_i,
+ input [31:0] dat_i,
+ input [3:0] sel_i,
+ output [31:0] dat_o,
+ output ack_o);
+
+ reg [31:0] distram [0:1<<(AWIDTH-1)];
+
+ always @(posedge clk_i)
+ begin
+ if(stb_i & we_i & sel_i[3])
+ distram[adr_i][31:24] <= dat_i[31:24];
+ if(stb_i & we_i & sel_i[2])
+ distram[adr_i][24:16] <= dat_i[24:16];
+ if(stb_i & we_i & sel_i[1])
+ distram[adr_i][15:8] <= dat_i[15:8];
+ if(stb_i & we_i & sel_i[0])
+ distram[adr_i][7:0] <= dat_i[7:0];
+ end // always @ (posedge clk_i)
+
+ assign dat_o = distram[adr_i];
+ assign ack_o = stb_i;
+
+endmodule // wb_ram_dist
+
+