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| author | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 | 
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 | 
| commit | fd3e84941de463fa1a7ebab0a69515b4bf2614cd (patch) | |
| tree | 3fa721a13d41d2c0451d663a59a220a38fd5e614 /fpga/usrp1/models/fifo_4k.v | |
| parent | 3b66804e41891e358c790b453a7a59ec7462dba4 (diff) | |
| download | uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.gz uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.bz2 uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.zip | |
Removed copy of FPGA source files.
Diffstat (limited to 'fpga/usrp1/models/fifo_4k.v')
| -rw-r--r-- | fpga/usrp1/models/fifo_4k.v | 24 | 
1 files changed, 0 insertions, 24 deletions
| diff --git a/fpga/usrp1/models/fifo_4k.v b/fpga/usrp1/models/fifo_4k.v deleted file mode 100644 index 1fa4ba0a7..000000000 --- a/fpga/usrp1/models/fifo_4k.v +++ /dev/null @@ -1,24 +0,0 @@ - - -module fifo_4k -  (  input [15:0] data, -     input 	wrreq, -     input 	rdreq, -     input 	rdclk, -     input 	wrclk, -     input 	aclr, -     output [15:0] q, -     output 	 rdfull, -     output 	 rdempty, -     output [11:0] rdusedw, -     output 	 wrfull, -     output 	 wrempty, -     output [11:0]  wrusedw -     ); - -fifo #(.width(16),.depth(4096),.addr_bits(12)) fifo_4k  -  ( data, wrreq, rdreq, rdclk, wrclk, aclr, q, -    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw); -    -endmodule // fifo_1k -    | 
