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| author | Ian Buckley <ianb@server2.(none)> | 2010-09-01 00:44:39 -0700 |
|---|---|---|
| committer | Ian Buckley <ianb@server2.(none)> | 2010-09-01 00:44:39 -0700 |
| commit | f18bf439ad1456452532285eedd131c54065213c (patch) | |
| tree | 20944eec77bfb9c6419ef5595c08dc27ca92042a | |
| parent | 492c5d53c31dd403817a27c6b25c30f8e089693b (diff) | |
| download | uhd-f18bf439ad1456452532285eedd131c54065213c.tar.gz uhd-f18bf439ad1456452532285eedd131c54065213c.tar.bz2 uhd-f18bf439ad1456452532285eedd131c54065213c.zip | |
Enhanced test bench to be more like real world application
| -rw-r--r-- | usrp2/extramfifo/ext_fifo_tb.sh | 3 | ||||
| -rw-r--r-- | usrp2/extramfifo/ext_fifo_tb.v | 18 |
2 files changed, 14 insertions, 7 deletions
diff --git a/usrp2/extramfifo/ext_fifo_tb.sh b/usrp2/extramfifo/ext_fifo_tb.sh index a56574102..dcfede37a 100644 --- a/usrp2/extramfifo/ext_fifo_tb.sh +++ b/usrp2/extramfifo/ext_fifo_tb.sh @@ -1 +1,2 @@ -fuse -prj ext_fifo_tb.prj -t work.glbl -t work.ext_fifo_tb -L unisims_ver -L xilinxcorelib_ver -o ext_fifo_tb +#fuse -prj ext_fifo_tb.prj -t work.glbl -t work.ext_fifo_tb -L unisims_ver -L xilinxcorelib_ver -o ext_fifo_tb +iverilog -c ext_fifo_tb.cmd -o ext_fifo_tb ext_fifo_tb.v diff --git a/usrp2/extramfifo/ext_fifo_tb.v b/usrp2/extramfifo/ext_fifo_tb.v index db5f31a9d..0eda89769 100644 --- a/usrp2/extramfifo/ext_fifo_tb.v +++ b/usrp2/extramfifo/ext_fifo_tb.v @@ -84,11 +84,17 @@ module ext_fifo_tb(); initial begin - repeat (20) @(negedge int_clk); + repeat (5) @(negedge int_clk); + dst_rdy_i <= 1; + + while (src_rdy_o !== 1) + @(negedge int_clk); // Fall through fifo, first output already valid if (dataout !== ref_dataout) - $display("Error: Expected %x, got %x",ref_dataout, dataout); + $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); + ref_dataout <= ref_dataout + src_rdy_o ; + // Decimate by 16 rate while (ref_dataout < 2000) begin @@ -96,7 +102,7 @@ module ext_fifo_tb(); ref_dataout <= ref_dataout + src_rdy_o ; dst_rdy_i <= src_rdy_o; if ((dataout !== ref_dataout) && src_rdy_o) - $display("Error: Expected %x, got %x",ref_dataout, dataout); + $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); @(negedge int_clk); dst_rdy_i <= 0; repeat(14) @(negedge int_clk); @@ -108,7 +114,7 @@ module ext_fifo_tb(); ref_dataout <= ref_dataout + src_rdy_o ; dst_rdy_i <= src_rdy_o; if ((dataout !== ref_dataout) && src_rdy_o) - $display("Error: Expected %x, got %x",ref_dataout, dataout); + $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); @(negedge int_clk); dst_rdy_i <= 0; repeat(6) @(negedge int_clk); @@ -120,7 +126,7 @@ module ext_fifo_tb(); ref_dataout <= ref_dataout + src_rdy_o ; dst_rdy_i <= src_rdy_o; if ((dataout !== ref_dataout) && src_rdy_o) - $display("Error: Expected %x, got %x",ref_dataout, dataout); + $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); @(negedge int_clk); dst_rdy_i <= 0; repeat(2) @(negedge int_clk); @@ -132,7 +138,7 @@ module ext_fifo_tb(); ref_dataout <= ref_dataout + src_rdy_o ; dst_rdy_i <= src_rdy_o; if ((dataout !== ref_dataout) && src_rdy_o) - $display("Error: Expected %x, got %x",ref_dataout, dataout); + $display("Error: Expected %x, got %x @%d",ref_dataout, dataout, $time); end // while (ref_dataout < 10000) |