put 64 bit timer for vita49 on the settings bus

3 files changed, 17 insertions, 8 deletions

diff --git a/timing/time_64bit.v b/timing/time_64bit.v
index c0a846e74..ab0c12be6 100644
--- a/timing/time_64bit.v
+++ b/timing/time_64bit.v
@@ -9,10 +9,13 @@ module time_64bit
      output [63:0] vita_time
      );
 
-   localparam 	   NEXT_TICKS = 0;
-   localparam 	   NEXT_SECS = 1;   
+   localparam 	   NEXT_TICKS = 1;
+   localparam 	   NEXT_SECS = 0;   
    localparam 	   ROLLOVER = TICKS_PER_SEC - 1;	   
    
+   reg [31:0] 	   seconds;
+   reg [31:0] 	   ticks;
+   wire 	   end_of_second;
    assign 	   vita_time = {seconds,ticks};
    
    wire [31:0] 	   next_ticks_preset;
@@ -28,11 +31,6 @@ module time_64bit
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(next_seconds_preset),.changed(set_on_pps_trig));
    
-   reg [31:0] 	   seconds;
-   reg [31:0] 	   ticks;
-   
-   wire 	   end_of_second;
-   
    always @(posedge clk)
      if(rst)
        set_on_next_pps <= 0;
diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v
index fd17a10a7..5b272c366 100755..100644
--- a/top/u2_core/u2_core.v
+++ b/top/u2_core/u2_core.v
@@ -135,6 +135,8 @@ module u2_core
    input sim_mode,
    input [3:0] clock_divider
    );
+
+   localparam SR_TIME64 = 192;
    
    wire [7:0] 	set_addr;
    wire [31:0] 	set_data;
@@ -159,6 +161,7 @@ module u2_core
    wire 	serdes_link_up;
    wire 	epoch;
    wire [31:0] 	irq;
+   wire [63:0] 	vita_time;
    
    // ///////////////////////////////////////////////////////////////////////////////////////////////
    // Wishbone Single Master INTERCON
@@ -560,7 +563,7 @@ module u2_core
       .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty),
       .debug_rx(debug_rx) );
    
-   // dummy_rx dsp_core_rx
+   // dumkmy_rx dsp_core_rx
    dsp_core_rx dsp_core_rx
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
@@ -631,6 +634,13 @@ module u2_core
    assign      RAM_CE1n = 0;
    assign      RAM_D[17:16] = 2'bzz;
    
+   // /////////////////////////////////////////////////////////////////////////
+   // VITA Timing
+
+   time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
+     (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .pps(pps_o), .vita_time(vita_time));
+   
    // /////////////////////////////////////////////////////////////////////////////////////////
    // Debug Pins
    
diff --git a/top/u2_rev3/Makefile b/top/u2_rev3/Makefile
index 4358d7c56..8b18550d1 100644
--- a/top/u2_rev3/Makefile
+++ b/top/u2_rev3/Makefile
@@ -171,6 +171,7 @@ serdes/serdes_fc_rx.v \
 serdes/serdes_fc_tx.v \
 serdes/serdes_rx.v \
 serdes/serdes_tx.v \
+timing/time_64bit.v \
 timing/time_receiver.v \
 timing/time_sender.v \
 timing/time_sync.v \